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[partial-reconfig] Multiple clocks
Hello,
I have a design which uses two clocks. The second clock is derived by a
divider from the first. Both use a dedicated BUFGMUX. However I run in
trouble with the SEL signal. I have LUT within the fixed part driving
the SEL inputs and further LUTs for driving the LT of the bus macros
within my reconf module. Nevertheless are both signals connected
resulting in a GLOBAL_LOGIC1_* crossing the boundary.
At the beginning I used BUFGs, but they are really BUFGMUX with a fixed
SEL ... and a GLOBAL_LOGIC1* ...
How can I use multiple clocks?
I attached my top level.
--
Dr. Thomas Reinemann www.uni-magdeburg.de/reineman
IMAT Public key available
Otto-von-Guericke-Universität Magdeburg
Universitätsplatz 2
39106 Magdeburg, Germany
-------------------------------------------------------------------------------
-- Design Units : clock_reconf
--
-- Filename : clock_reconf.vhdl
--
-- Purpose : simple partial reconfiguration example
-- Library :
--
-- Dependencies : IEEE.Std_Logic_1164, ieee.numeric_std, ieee.math_real
--
-- Sub Modules : vec2led, clock, clk_divider
-- Author : <thomas.reinemann@mb.uni-magdeburg.de>
-- Company :
-- Created : 2004-05-24
-- Last update: 2004-07-29
-- Platform :
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2004-05-24 1.0 threinem Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
entity clock_reconf is
port (
CLK_40MHZ_in : in STD_LOGIC;
PB_SWITCH : in STD_LOGIC_VECTOR (1 downto 0);
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
SEG1_2 : out STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end clock_reconf;
architecture struct of clock_reconf is
signal RESET, clk_160khz, clk_160khz_ls, CLK_40MHZ : std_logic;
signal seconds : STD_LOGIC_VECTOR (7 downto 0);
signal SEG1_INT_reconf, SEG2_INT_reconf : STD_LOGIC_VECTOR (7 downto 0);
signal SEG1_INT, SEG2_INT : STD_LOGIC_VECTOR (7 downto 0);
signal seconds_reconf : STD_LOGIC_VECTOR (7 downto 0);
signal ndir, dir : std_logic_vector (7 downto 0);
signal div_count : std_logic_vector (7 downto 0);
signal vcc_reconf, gnd_reconf : std_logic;
signal vcc_fixed, gnd_fixed : std_logic;
component clock_40Mhz
port (
reset, clk_40Mhz : in std_logic;
seconds, minutes : out std_logic_vector (7 downto 0));
end component;
component vec2led
port (
MEASURED_T : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
LCD_OUT1 : out STD_LOGIC_VECTOR (7 downto 0);
LCD_OUT2 : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component clk_divider
generic (
divider : integer);
port (
reset, clk_high : in std_logic;
clk_out : out std_logic);
end component;
component bm_v2
generic (
word_width : integer);
port (
LT, RT, LI, RI : in std_logic_vector (word_width - 1 downto 0);
O : out std_logic_vector (word_width - 1 downto 0));
end component;
component LUT1 is
generic (INIT: bit_vector := X"3");
port (O: out std_ulogic;
I0: in std_ulogic);
end component;
component IBUFG is
port ( I:in std_logic;
O: out std_logic);
end component;
component BUFG is
port ( I:in std_logic;
O: out std_logic);
end component;
component CLKDLL is
port ( CLKIN: in std_logic;
CLKFB: in std_logic;
RST: in std_logic;
CLK0: out std_logic;
CLK90: out std_logic;
CLK180: out std_logic;
CLK270: out std_logic;
CLKDV: out std_logic;
CLK2X: out std_logic;
LOCKED: out std_logic);
end component;
component BUFGMUX
port ( O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic );
end component;
begin
RESET <= PB_SWITCH(0);
Seg1 <= Seg1_int;
Seg2 <= Seg2_int;
Seg1_2 <= Seg1_int;
--Seg2_2 <= Seg2_int;
BUFG_1: BUFGMUX
port map (
I0 => clk_160khz_ls,
I1 => clk_160khz_ls,
S => vcc_fixed,
O => clk_160khz);
BUFG_2: BUFGMUX
port map (
I0 => CLK_40MHZ_in,
I1 => CLK_40MHZ_in,
S => vcc_fixed,
O => CLK_40MHZ);
clk_divider_1: clk_divider
generic map (
divider => 125)
port map (
reset => reset,
clk_high => CLK_40MHZ,
clk_out => clk_160khz_ls);
Internal_GND_reconfig: LUT1
generic map (
INIT => b"00")
port map (
O => gnd_reconf,
I0 => vcc_reconf);
Internal_VCC_reconfig: LUT1
generic map (INIT => b"11")
port map (
O => vcc_reconf,
I0 => gnd_reconf);
Internal_GND_fixed: LUT1
generic map (
INIT => b"00")
port map (
O => gnd_fixed,
I0 => vcc_fixed);
Internal_VCC_fixed: LUT1
generic map (INIT => b"11")
port map (
O => vcc_fixed,
I0 => gnd_fixed);
clock_1: clock_40Mhz
port map (
reset => reset,
clk_40Mhz => clk_160khz,
seconds => seconds,
minutes => led);
-- bus macros to lock routes during partial reconfiguration
bm_v2_1: bm_v2
generic map (
word_width => 8)
port map (
RT => ndir,
LT => vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf,
RI => seconds,
LI => vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf & vcc_reconf,
O => seconds_reconf);
bm_v2_2: bm_v2
generic map (
word_width => 8)
port map (
RT => dir,
LT => gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf,
RI => dir,
LI => SEG1_INT_reconf,
O => seg1_int);
bm_v2_3: bm_v2
generic map (
word_width => 8)
port map (
RT => dir,
LT => gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf & gnd_reconf,
RI => dir,
LI => SEG2_INT_reconf,
O => seg2_int);
srr_40: process (CLK_40MHZ)
begin -- process srr
if CLK_40MHZ'event and CLK_40MHZ = '1' then -- rising clock edge
dir <= not (PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1));
end if;
end process srr_40;
srr_160: process (clk_160khz)
begin -- process srr
if clk_160khz'event and clk_160khz = '1' then -- rising clock edge
ndir <= PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1);
end if;
end process srr_160;
-- dir <= not (PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1) & PB_SWITCH(1));
vec_conv: vec2led
port map(
MEASURED_T => seconds_reconf,
CLK => clk_160khz,
RESET => RESET,
LCD_OUT1 => SEG1_INT_reconf,
LCD_OUT2 => SEG2_INT_reconf);
end struct;