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[partial-reconfig] Problem with Bus macro in Virtex-II
I am using ISE6.2i, and Virtex-II X2CV1000. When i use:
"ngdbuild -modular initial top.ngc"
The tool reports some errors with the bus macro, like this:
Reading component libraries for design expansion...
Loading device for application ngdbuild from file '2v1000.nph' in environment
C:/Xilinx.
Loading macro from file "E:\John\exemplo\top\inicial/bm_4b_v2.nmc".
ERROR:NgdBuild:76 - File "E:\John\exemplo\top\inicial/bm_4b_v2.nmc" cannot
be merged into block "BM_reconfig_1_to_capture_result"
(TYPE="bm_4b_v2")because one or more pins on the block, including pin
"LI<3>", were not found in the file. Please make sure that all pins on
the instantiated component match pins in the lower-level design block
(irrespective of case). If there are bussed pins on this block, make sure
that the upper-level and lower-level netlists use the same bus-naming
convention.
I send you the top.vhd for help. I´m trying to resolve this problem but i
dont find the solution yet.
John Edward Esquiagola Aranda
Laboratorio de Microeletrônica
Escola Politecnica da Universidade de São Paulo
library IEEE;
use ieee.std_logic_1164.all;
--library exemplar;
--use exemplar.exemplar.all;
entity top is
port(
reset: in std_logic;
clock: in std_logic;
input_A: in std_logic_vector(1 downto 0);
input_B: in std_logic_vector(1 downto 0);
input_C: in std_logic_vector(2 downto 0);
get_data: in std_logic;
displayA: out std_logic_vector(6 downto 0);
-- modificação JEEA
VCC_fixed: in std_logic;
GND_fixed: in std_logic;
VCC_reconfig_1: in std_logic;
GND_reconfig_1: in std_logic;
VCC_reconfig_2: in std_logic;
GND_reconfig_2: in std_logic
);
end top;
architecture arch of top is
-- Capture: this module captures input data and translates reconfig data to display the result
component capture is
port (
input_A: in std_logic_vector(1 downto 0);
input_B: in std_logic_vector(1 downto 0);
input_C: in std_logic_vector(2 downto 0);
output_A: out std_logic_vector(1 downto 0);
output_B: out std_logic_vector(1 downto 0);
output_C: out std_logic_vector(2 downto 0);
reset: in std_logic;
clock : in std_logic;
get_data: in std_logic; -- this button pushes data to reconfig module
input_reconfig: in std_logic_vector(3 downto 0);
displayA: out std_logic_vector(6 downto 0)
);
end component;
------ RECONFIG ------
-- 2 bit adder -> 3 bit output
component adder2bit is
port(
input_A: in std_logic_vector(1 downto 0);
input_B: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end component;
-- 3 bit adder -> 4 bit output
component adder3bit is
port(
input_A: in std_logic_vector(2 downto 0);
input_B: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end component;
------ END OF RECONFIG ------
-- Bus macro
component bm_4b_v2 is
port(
LI: in std_logic_vector(3 downto 0);
LT: in std_logic_vector(3 downto 0);
RI: in std_logic_vector(3 downto 0);
RT: in std_logic_vector(3 downto 0);
O: out std_logic_vector(3 downto 0)
);
end component;
------ LUT -----
-- modificação JEEA
--component LUT1 is
-- generic (INIT: bit_vector := X"3");
-- port (O: out std_ulogic;
-- I0: in std_ulogic);
--end component;
-- Buffers instantiate. They are used to attached clock on the design.
component IBUFG
is port (
I:in std_logic;
O: out std_logic);
end component;
component BUFG is port (
I:in std_logic;
O: out std_logic);
end component;
component CLKDLL is port (
CLKIN: in std_logic;
CLKFB: in std_logic;
RST: in std_logic;
CLK0: out std_logic;
CLK90: out std_logic;
CLK180: out std_logic;
CLK270: out std_logic;
CLKDV: out std_logic;
CLK2X: out std_logic;
LOCKED: out std_logic);
end component;
component INV is port (
I:in std_logic;
O: out std_logic);
end component;
signal dll_clk_in : std_logic;
signal dll_clk_out : std_logic;
signal reset_dll : std_logic;
signal clk_top: std_logic;
-- "Top" signals
-- "Going Nowhere" - keeps the bus macro from being removed when not fully used
signal going_nowhere1, going_nowhere2, going_nowhere3: std_logic;
-- VCC / GND signals
-- modificação JEEA
--signal VCC_fixed: std_logic;
--signal GND_fixed: std_logic;
--signal VCC_reconfig_1: std_logic;
--signal GND_reconfig_1: std_logic;
--signal VCC_reconfig_2: std_logic;
--signal GND_reconfig_2: std_logic;
-- Reconfig 1 Signals
-- Input A
signal inBM_reconfig_1_input_A: std_logic_vector(1 downto 0);
signal outBM_reconfig_1_input_A: std_logic_vector(1 downto 0);
-- Input B
signal inBM_reconfig_1_input_B: std_logic_vector(1 downto 0);
signal outBM_reconfig_1_input_B: std_logic_vector(1 downto 0);
-- Input C - Sinal de passagem pela area "reconfig 1"
signal inBM_reconfig_1_pass_C: std_logic_vector(2 downto 0);
signal outBM_reconfig_1_pass_C: std_logic_vector(2 downto 0);
-- Result - Sinal de passagem pela area "reconfig 1"
-- signal outBM_reconfig_1_pass_result: std_logic_vector(3 downto 0); -- Este sinal já foi declarado, só coloquei ele aqui para deixar claro que ele é o sinal de entrada da BM que passa do reconfig 1 para o capture
signal outBM_capture_pass_result: std_logic_vector(3 downto 0);
-- Reconfig 2 Signals
-- Soma de A e B
signal inBM_reconfig_2_input_A: std_logic_vector(2 downto 0);
signal outBM_reconfig_2_input_A: std_logic_vector(2 downto 0);
-- Sinal vindo direto de "capture"
-- signal outBM_reconfig_1_pass_C: std_logic_vector(2 downto 0); -- Este sinal já foi declarado, só coloquei ele aqui para deixar claro que ele é o sinal de entrada da BM que passa do reconfig 1 para o reconfig 2
signal outBM_reconfig_2_input_C: std_logic_vector(2 downto 0);
-- Result - Sinal de saida da área reconfig 2 para a área reconfig 1
signal inBM_reconfig_1_pass_result: std_logic_vector(3 downto 0);
signal outBM_reconfig_1_pass_result: std_logic_vector(3 downto 0);
begin
-- Internal_GND_fixed: LUT1
-- generic map (INIT => b"00")
-- port map (O=>GND_fixed, I0=>GND_fixed); -- modified by moraes input receiving output
-- Internal_VCC_fixed: LUT1
-- generic map (INIT => b"11")
-- port map (O=>VCC_fixed, I0=>VCC_fixed);
-- Internal_GND_reconfig_1: LUT1
-- generic map (INIT => b"00")
-- port map (O=>GND_reconfig_1, I0=>GND_reconfig_1);
-- Internal_VCC_reconfig_1: LUT1
-- generic map (INIT => b"11")
-- port map (O=>VCC_reconfig_1, I0=> VCC_reconfig_1);
-- Internal_GND_reconfig_2: LUT1
-- generic map (INIT => b"00")
-- port map (O=>GND_reconfig_2, I0=>GND_reconfig_2);
-- Internal_VCC_reconfig_2: LUT1
-- generic map (INIT => b"11")
-- port map (O=>VCC_reconfig_2, I0=> VCC_reconfig_2);
-- CLKDLL code
ibuf_dll: IBUFG port map (I => clock, O => dll_clk_in);
dll_1: CLKDLL port map (CLKIN => dll_clk_in, CLKFB => clk_top, CLK0 => dll_clk_out, RST => reset_dll);
global_clk: BUFG port map (I => dll_clk_out, O => clk_top);
-- reset_inversor: INV port map (I=>reset, O=> reset_dll);
reset_dll <= not reset; -- CLKDLL: reset is actived in 1;
-- Reconfig 1 - Signal A / B capture to reconfig 1 / Adder2bit Input Bus Macro
BM_capture_to_reconfig_1_Input_AB: bm_4b_v2 port map
(LI(3)=> inBM_reconfig_1_input_A(1),
LI(2)=> inBM_reconfig_1_input_A(0),
LI(1)=> inBM_reconfig_1_input_B(1),
LI(0)=> inBM_reconfig_1_input_B(0),
LT(3) => GND_fixed, -- enable all left tristates
LT(2) => GND_fixed,
LT(1) => GND_fixed,
LT(0) => GND_fixed,
RI(3) => GND_reconfig_1,-- no entries this side of bm
RI(2) => GND_reconfig_1,
RI(1) => GND_reconfig_1,
RI(0) => GND_reconfig_1,
RT(3) => VCC_reconfig_1, -- disable all right tri-sates
RT(2) => VCC_reconfig_1,
RT(1) => VCC_reconfig_1,
RT(0) => VCC_reconfig_1,
O(3) => outBM_reconfig_1_input_A(1),
O(2) => outBM_reconfig_1_input_A(0),
O(1) => outBM_reconfig_1_input_B(1),
O(0) => outBM_reconfig_1_input_B(0)
);
-- Reconfig 1 - Signal C capture to reconfig 1 Bus Macro
BM_capture_to_reconfig_1_Input_C: bm_4b_v2 port map
(LI(3)=> GND_fixed,
LI(2)=> inBM_reconfig_1_pass_C(2),
LI(1)=> inBM_reconfig_1_pass_C(1),
LI(0)=> inBM_reconfig_1_pass_C(0),
LT(3) => GND_fixed, -- enable all left tristates
LT(2) => GND_fixed,
LT(1) => GND_fixed,
LT(0) => GND_fixed,
RI(3) => GND_reconfig_1,-- no entries this side of bm
RI(2) => GND_reconfig_1,
RI(1) => GND_reconfig_1,
RI(0) => GND_reconfig_1,
RT(3) => VCC_reconfig_1, -- disable all right tri-sates
RT(2) => VCC_reconfig_1,
RT(1) => VCC_reconfig_1,
RT(0) => VCC_reconfig_1,
O(3) => going_nowhere1,
O(2) => outBM_reconfig_1_pass_C(2),
O(1) => outBM_reconfig_1_pass_C(1),
O(0) => outBM_reconfig_1_pass_C(0)
);
-- Reconfig 2 - Adder2bit Output Bus Macro / Adder3bit Input A
BM_reconfig_1_to_reconfig_2_Input_A: bm_4b_v2 port map
(LI(3)=> GND_reconfig_1,
LI(2)=> inBM_reconfig_2_input_A(2),
LI(1)=> inBM_reconfig_2_input_A(1),
LI(0)=> inBM_reconfig_2_input_A(0),
LT(3) => GND_reconfig_1, -- enable all left tristates
LT(2) => GND_reconfig_1,
LT(1) => GND_reconfig_1,
LT(0) => GND_reconfig_1,
RI(3) => GND_reconfig_2,-- no entries this side of bm
RI(2) => GND_reconfig_2,
RI(1) => GND_reconfig_2,
RI(0) => GND_reconfig_2,
RT(3) => VCC_reconfig_2, -- disable all right tri-sates
RT(2) => VCC_reconfig_2,
RT(1) => VCC_reconfig_2,
RT(0) => VCC_reconfig_2,
O(3) => going_nowhere2,
O(2) => outBM_reconfig_2_input_A(2),
O(1) => outBM_reconfig_2_input_A(1),
O(0) => outBM_reconfig_2_input_A(0)
);
-- Reconfig 2 - Signal C reconfig 1 to reconfig 2 / Adder3bit Input C
BM_reconfig_1_to_reconfig_2_Input_C: bm_4b_v2 port map
(LI(3)=> GND_reconfig_1,
LI(2)=> outBM_reconfig_1_pass_C(2),
LI(1)=> outBM_reconfig_1_pass_C(1),
LI(0)=> outBM_reconfig_1_pass_C(0),
LT(3) => GND_reconfig_1, -- enable all left tristates
LT(2) => GND_reconfig_1,
LT(1) => GND_reconfig_1,
LT(0) => GND_reconfig_1,
RI(3) => GND_reconfig_2,-- no entries this side of bm
RI(2) => GND_reconfig_2,
RI(1) => GND_reconfig_2,
RI(0) => GND_reconfig_2,
RT(3) => VCC_reconfig_2, -- disable all right tri-sates
RT(2) => VCC_reconfig_2,
RT(1) => VCC_reconfig_2,
RT(0) => VCC_reconfig_2,
O(3) => going_nowhere3,
O(2) => outBM_reconfig_2_input_C(2),
O(1) => outBM_reconfig_2_input_C(1),
O(0) => outBM_reconfig_2_input_C(0)
);
-- Reconfig 2 - Signal result reconfig 2 to reconfig 1 / Adder3bit Output
BM_reconfig_2_to_reconfig_1_result: bm_4b_v2 port map
(LI(3) => GND_fixed,-- no entries this side of bm
LI(2) => GND_fixed,
LI(1) => GND_fixed,
LI(0) => GND_fixed,
LT(3) => VCC_reconfig_1, -- enable all left tristates
LT(2) => VCC_reconfig_1,
LT(1) => VCC_reconfig_1,
LT(0) => VCC_reconfig_1,
RI => inBM_reconfig_1_pass_result,
RT(3) => GND_reconfig_2, -- disable all right tri-sates
RT(2) => GND_reconfig_2,
RT(1) => GND_reconfig_2,
RT(0) => GND_reconfig_2,
O => outBM_reconfig_1_pass_result
);
-- Reconfig 1 - Signal result reconfig 1 to capture / LCD input
BM_reconfig_1_to_capture_result: bm_4b_v2 port map
(LI(3) => GND_fixed,-- no entries this side of bm
LI(2) => GND_fixed,
LI(1) => GND_fixed,
LI(0) => GND_fixed,
LT(3) => VCC_fixed, -- enable all left tristates
LT(2) => VCC_fixed,
LT(1) => VCC_fixed,
LT(0) => VCC_fixed,
RI => outBM_reconfig_1_pass_result,
RT(3) => GND_reconfig_1, -- disable all right tri-sates
RT(2) => GND_reconfig_1,
RT(1) => GND_reconfig_1,
RT(0) => GND_reconfig_1,
O => outBM_capture_pass_result
);
Fixed_Logic: capture
port map (input_A => input_A,
input_B => input_B,
input_C => input_C,
output_A => inBM_reconfig_1_input_A,
output_B => inBM_reconfig_1_input_B,
output_C => inBM_reconfig_1_pass_C,
reset => reset,
clock => clk_top,
get_data => get_data,
input_reconfig => outBM_capture_pass_result,
displayA => displayA
);
Reconfig_1: adder2bit
port map (input_A => outBM_reconfig_1_input_A,
input_B => outBM_reconfig_1_input_B,
output => inBM_reconfig_2_input_A
);
Reconfig_2: adder3bit
port map (input_A => outBM_reconfig_2_input_A,
input_B => outBM_reconfig_2_input_C,
output => inBM_reconfig_1_pass_result
);
end arch;