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Re: [partial-reconfig] Problem with Bus macro in Virtex-II
John Williams wrote:
> Hi John
>
> jedward@lme.usp.br wrote:
>
>> I am using ISE6.2i, and Virtex-II X2CV1000. When i use:
>>
>> "ngdbuild -modular initial top.ngc"
>>
>> The tool reports some errors with the bus macro, like this:
>>
>> Reading component libraries for design expansion...
>> Loading device for application ngdbuild from file '2v1000.nph' in
>> environment
>> C:/Xilinx.
>> Loading macro from file "E:\John\exemplo\top\inicial/bm_4b_v2.nmc".
>> ERROR:NgdBuild:76 - File "E:\John\exemplo\top\inicial/bm_4b_v2.nmc"
>> cannot
>> be merged into block "BM_reconfig_1_to_capture_result"
>> (TYPE="bm_4b_v2")because one or more pins on the block, including pin
>> "LI<3>", were not found in the file.
>
>
> There is a Xilinx answer record on this one:
>
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14848
>
>
> Basically it's to do with signal vectors using the '< >' vs '( )'
> synatx. If I remember rightly, I just hand edited the bus macro file in
> hexedit, and changed the characters appropriately.
A more appropriate way is to use the xdl command, to recompile the bus
macro, e.g.
xdl -ncd2xdl bm_4b_v2.nmc
this will result in a human readable xdl file. Just now you can correct
an error in the Virtex bus macro, adding a PIP for the TBUF of TNET(3)
or may be TNET<3> or ... :-). Than compile it
xdl -xdl2ncd bm_4b_v2.xdl
Here, you obtain bm_4b_v2.ncd, simply rename it to bm_4b_v2.nmc. Well
done, now you will have less problems with strange routing of the TNET(3).
BTW, the Virtex Pro (bm_4b_v2p.nmc) suffers from this error too.
Regards,
--
Dr. Thomas Reinemann www.uni-magdeburg.de/reineman
IMAT Public key available
Otto-von-Guericke-Universität Magdeburg
Universitätsplatz 2
39106 Magdeburg, Germany
# =======================================================
# XDL NCD CONVERSION MODE $Revision: 1.39.4.1 $
# time: Wed Jul 28 10:42:39 2004
# cmd: xdl -ncd2xdl bm_4b_v2.nmc
# =======================================================
# =======================================================
# The syntax for the design statement is:
# design <design_name> <part> <ncd version>;
# or
# design <design_name> <device> <package> <speed> <ncd_version> ;
# =======================================================
design "__XILINX_NMC_MACRO" x2v250fg256-5 v2.38 ;
# =======================================================
# The syntax for modules is:
# module <name> <inst_name> ;
# port <name> <inst_name> <inst_pin> ;
# .
# .
# instance ... ;
# .
# .
# net ... ;
# .
# .
# endmodule <name> ;
# =======================================================
# =======================================================
# MODULE of "bm_4b_v2"
# =======================================================
module "bm_4b_v2" "t1A_<3>" , cfg "_SYSTEM_MACRO::FALSE" ;
port "LI<3>" "t1A_<3>" "I" ;
port "LT<3>" "t1A_<3>" "T" ;
port "RI<3>" "t1E_<3>" "I" ;
port "RT<3>" "t1E_<3>" "T" ;
port "LI<2>" "t2B_<2>" "I" ;
port "LT<2>" "t2B_<2>" "T" ;
port "RI<2>" "t2F_<2>" "I" ;
port "RT<2>" "t2F_<2>" "T" ;
port "LI<1>" "t3C_<1>" "I" ;
port "LT<1>" "t3C_<1>" "T" ;
port "RI<1>" "t3G_<1>" "I" ;
port "RT<1>" "t3G_<1>" "T" ;
port "LI<0>" "t4D_<0>" "I" ;
port "LT<0>" "t4D_<0>" "T" ;
port "RI<0>" "t4H_<0>" "I" ;
port "RT<0>" "t4H_<0>" "T" ;
port "O<3>" "t1A_<3>" "O" ;
port "O<2>" "t2B_<2>" "O" ;
port "O<1>" "t3C_<1>" "O" ;
port "O<0>" "t4D_<0>" "O" ;
inst "t1A_<3>" "TBUF" , placed R24C7 TBUF_X12Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t1E_<3>" "TBUF" , placed R24C9 TBUF_X16Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t2B_<2>" "TBUF" , placed R24C7 TBUF_X12Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t2F_<2>" "TBUF" , placed R24C9 TBUF_X16Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t3C_<1>" "TBUF" , placed R24C8 TBUF_X14Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t3G_<1>" "TBUF" , placed R24C10 TBUF_X18Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t4D_<0>" "TBUF" , placed R24C8 TBUF_X14Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t4H_<0>" "TBUF" , placed R24C10 TBUF_X18Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
net "TNET<3>" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t1A_<3>" O ,
outpin "t1E_<3>" O ,
pip R24C7 TOUT0 -> TBUF0 ,
pip R24C6 TBUF3 =- TBUF3_E ,
pip R24C9 TOUT0 -> TBUF2 ,
# net "TNET<3>" loads=0 drivers=2 pips=2 rtpips=0
;
net "TNET<2>" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t2B_<2>" O ,
outpin "t2F_<2>" O ,
pip R24C7 TOUT1 -> TBUF3 ,
pip R24C7 TBUF3 =- TBUF3_E ,
pip R24C9 TOUT1 -> TBUF1 ,
# net "TNET<2>" loads=0 drivers=2 pips=3 rtpips=0
;
net "TNET<1>" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t3C_<1>" O ,
outpin "t3G_<1>" O ,
pip R24C8 TOUT1 -> TBUF3 ,
pip R24C8 TBUF3 =- TBUF3_E ,
pip R24C10 TOUT1 -> TBUF1 ,
# net "TNET<1>" loads=0 drivers=2 pips=3 rtpips=0
;
net "TNET<0>" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t4D_<0>" O ,
outpin "t4H_<0>" O ,
pip R24C8 TOUT0 -> TBUF2 ,
pip R24C9 TBUF3 =- TBUF3_E ,
pip R24C10 TOUT0 -> TBUF0 ,
# net "TNET<0>" loads=0 drivers=2 pips=3 rtpips=0
;
endmodule "bm_4b_v2" ;
# ================================================
# MODULE INSTANCEs
# ================================================
# ================================================
# SUMMARY
# Number of Module Defs: 1
# Number of Module Insts: 0
# Number of Primitive Insts: 0
# Number of Nets: 0
# ================================================