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Re: [partial-reconfig] Bus macro creation
John Esquiagola wrote:
> Hi Tom,
>
> I did my special bus macro. After the recompilation process, i only
> modified the position of the column and the Buffer associated.
>
> original:
>
> inst "t1A_(3)" "TBUF" , placed R24C7 TBUF_X12Y0 ,
> cfg "TINV::T IINV::I _SUPERBEL::TRUE"
>
> modified:
>
> inst "t1A_(3)" "TBUF" , placed R24C3 TBUF_X4Y0 ,
> cfg "TINV::T IINV::I _SUPERBEL::TRUE"
>
> Finally, when i recompiled to ncd, the routing is no complete then i did
> manual routing of the lines using FPGA EDITOR.
You can do this within the xdl-file, by adding TBUF3_E to extend the
long line. A long line is divided in some parts, which can be
concatenated by TBUF3_E.
The attached bus macro xdl has an additional TBUF on TNET(3).
The following answers my own question, from the initial posting.
>>I need a special bus macro. I have three reconf modules a, b , c from
>>left to right. The signals shall be driven in a and read in b and c. In
>>a first step I recompiled the Xilinx bus macro, and want now to edit it.
>>But I have no imagine what the pips are?
PIPs are Programmable Interconnection points (Xilinx has a glossary).
Pips are used to drive und read long lines. Tbuf outputs are connected
to long lines via Pips, and long lines are extended via pips (see TBUF3_E).
--
Dr. Thomas Reinemann www.uni-magdeburg.de/reineman
IMAT Public key available
Otto-von-Guericke-Universität Magdeburg
Universitätsplatz 2
39106 Magdeburg, Germany
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