[partial-reconfig] Unguided slices

[Miguel Silva <mlms@xxxxxxxx>]

Hello

I'm trying to perform some partial reconfiguration experiments using  
EDK/ISE 6.2 on Virtex2 PRO. My design includes 3 modules, one 
reconfigurable and 2 fixed. One fixed module includes the PPC and some 
of the basic peripherals, one of the peripherals is included in the 
other fixed module the connection between the two is made is made 
without  the TBUFs, but that shouldn't pose a problem according to a 
recent article from Xilinx.
My problem is this, when I reach the assembling stage my final design, 
when I manage to avoid the recurrent 
"FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137" and  
"FATAL_ERROR:Ncd:basncsignal.c:283:1.39.8.2" errors, always as some 
unrouted lines that I canīt route even and in the FPGA_EDITOR, the 
problem seems to come from the fact that in the main module there are 
always some unguided slices, I tried changing the parameters of ngdbuild 
and map but I only managed to change the slices that are unguided.

My questions are these:

As anyone made successful attempts at partial reconfiguration with 
similar designs, or at least one with PPC and peripherals?

Is it essential to get a 100% guided design or is it possible to achieve 
partial reconfiguration without it?

The slices seems to be unguided because their structure changes from the 
module stage to the assemble stage, registers are missing or change 
places, any ideas on why this could be happening?

Thanks

Miguel Silva
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