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Hello EveryBody,
I think you people might have already received my
introduction mail
Now I will try and ask some of the Qs I am
facing
I will try to brief you my problem
I have 2 parts Part A and Part B mapped in an FPGA
through Modular Design flow of Xilinx.
Now if I try to reconfigure configuration memory of
Part B through Part A and make it run is that possible....?
I want to completely reconfigure the Part B with a
new bitstream of complete logic
according to what I have understood from the app
notes of xilinx about ICAP ports is that it can be used for active
reconfiguration but only for some embedded parts of the FPGA like DCM and change
its IO configuration or multiplier configuration on fly and reuse
it.
Can anybody give me some more info.?
one more thing does it require any other tool set
other than ISE and Modelsim
Thanks in advance and I will try to read xapp290
4-5 times carefully
Thanks once again for the suggessions
Rgds
Kedar |