Re: [partial-reconfig] Putting logic into bus macros

[Armando Astarloa <jtpascua@xxxxxxxxx>]

Hello Tom,

         You can start with an HDL(VHDL, VERILOG) design, using the 
appropriate location attributes (constrains).
         Synthesize with IOB option enabled and P&R.

         After that with the FPGA editor:
                 - Save as macro
                 - Delete & unroute IOB
                 - Add macro external pins to the unrouted comp. pins with 
the appropiate port names.
                 - Set a component as the reference point for the macro.

         Bye,

                 Armando


At 13:35 05/11/2004 +0100, you wrote:
>Hello,
>
>I want to put some logic into a bus macro. Is there a possibility to use 
>place and route tools and to aviod handwork?
>
>Bye Tom
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>partial-reconfig@itee.uq.edu.au
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Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
Tecnología Electrónica
Departamento de Electrónica y Telecomunicaciones
Escuela Superior de Ingenieros - Email: jtpascua@bi.ehu.es
Ald. de Urquijo s/n             Tel.: 34 - 94 - 601 73 04
48013 BILBAO (SPAIN)    Fax.: 34 - 94 - 601 42 59
URL : http://det.bi.ehu.es/~apert
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