[partial-reconfig] Intro, and a few questions...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hi...

I'm working on my MS Thesis which is still very much in its infancy so
there's no title yet... what I do know is that it will involve FPGA
Reconfiguration... I have a few vague ideas about which way I'll go...
perhaps an ALU accepting RISC-style instructions with the configurations
changing based on what the instructions to follow are, or perhaps having
configurations aimed towards executing loops... Any other ideas would be
welcome... I'm looking forward to having it all wrapped up soon and head
for a Doctorate in the UK or the US ( I'm presently in Pakistan and
working at CE&ME, NUST ... ) ...

I've modified the xapp290.zip design a little, expanding the adder and
subtractor to cover 12 slices each and replacing the multiplier and
shifter with AND and OR modules, for simplicity... There are a couple of
questions I had regarding the xapp290 design...

1) I thought we were supposed to place the Bus Macros right on the
boundaries on the Reconfigurable module and that they would therefore
naturally fall on a multiple of 4 along the x-axis, but in the .ucf file
for the Top-Levels in xapp290, the first BM falls at x = 6 and the other
on x = 20, which is a multiple of 4 but not on the boundary between
"mult" and "sub", which is at x=24... how do we explain that? In my own
design I've got them on the edges and they work fine, but I can't figure
out why the Xilinx design breaks its own rules...

2) Can someone explain the "triR1, triL1, triR2, triL2" inputs and the
"tribusR1, tribusL1, tribusR2, tribusL2" wires? Why do we need these
inputs to determine the direction of data flow in the BMs? For instance,
in the BM between the adder and the multiplier, why can't we provide the
adder outputs to LI (which xapp290 does anyhow), provide LT with
all-ones (making sure that LI goes to the output), and Grounding RI and
RT? Since RT is zero, RI isn't selected and the output goes to
high-impedance from the "mult" side... I might've got the details
regarding the working of tri-state buffers all wrong, but I still can't
figure out the need to have external inputs to the design for deciding
the direction of data flow... I've tried doing what I suggested above,
but before I get too far, viewing the design in Floorplanner shows that
one buses on one side are fine, but on the other they seem to be
connected to each other, i.e. the top 4-bit bus is connected to the one
below it, which is also connected to the two below it, and so on and so
forth... I also tried using this method in my design that works, and one
16-bit bus performs fine, with the outputs from the subtractor going to
the reconfigurable module and also to an output pin, but the other
16-bit bus does nothing at all...

I'd appreciate help on these problems...

Thanks!

Sincerely,
Umar

P.S. Nice job with the mailing list... :)
-- 
  Umar Mushtaq
  misfit_05@fastmail.fm

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