RE: [partial-reconfig] About Module design

["luyi" <yilu@xxxxxxxxxxxxxx>]

Hi, Umar:

Thank you for your reply. I think the problem in my test program is that is
so simple (without any internal communication signals between 2 modules).
Now, I just add some internal signals, everything is ok. But I don't know
why the internal signal must be here.

Regards.
luyi

-----Original Message-----
From: owner-partial-reconfig@itee.uq.edu.au
[mailto:owner-partial-reconfig@itee.uq.edu.au] On Behalf Of Umar Mushtaq
Sent: Thursday, 25 November 2004 4:13 PM
To: partial-reconfig@itee.uq.edu.au
Subject: Re: [partial-reconfig] About Module design

Hi Luyi...

I had the same problems initially, but de-selecting the "add buffer"
thingie for the modules took care of it... However, I still get the
warnings you referred to, but the design still works okay...

Some of the more experienced posters will probably tell you what's
wrong... I wonder where they are though... still awaiting a response for
my post...

:)

Sincerely,
Umar
-- 
  Umar Mushtaq
  misfit_05@fastmail.fm

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