Re: [partial-reconfig] Probing for research topics

[Ron Sass <rsass@xxxxxxxxxxx>]

Sean, Jens, Jingzhao, John --

Coincidentally I've been talking to Jingzhao on the uClinux
mailing list and I too am very interested in working out the
practical details of partial reconfiguration.  I'm not as
far any of you but no time like the present to learn.

Which ERSA paper are people talking about?  I've got a copy
of the 2004 proceedings but there doesn't seem to be an
electronic copy of that conference series :( :( so I only
get to read a few papers that I happen to pick up via some
other route.

Ron


> Hi, Sean,
> 
> I am very interested in your thesis even though I don't understand 
> Germany. :-)
> 
> Also, I am very interested in your designs if you are willing to share 
> them. I am working on this issue these days as well using MicroBlaze. I 
> follow the module-based partial reconfiguration flow. I tried to put 
> MicroBlaze in a module and then used it to reconfigure another module.
> 
> Till now, I have successfully run through the module-based design flow 
> for MicroBlaze. However, I got stuck when creating the partial 
> reconfiguration bitstreams. Whenever I put
> 
> AREA_group "AG_mb" MODE = RECONFIG ;
> 
> I got an internal error when running par at the module-assemble stage. I 
> opened a case with Xilinx. They said that this is caused by a bug in the 
> par tool. They are now looking into my design to find out the problem.
> 
> I would like to share my design if any one is interested in looking into 
> it as well. It is for Virtex-II Pro vp7 on ML300. I have a Spartan-3 400 
> board. But this chip is too small. I am going to have Virtex-4 as well. 
> However, both Spartan-3 and Virtex-4 do NOT have TBUF. I don't know how 
> to communicate between different modules without TBUFs, which are 
> required to create bus macros. So, I will use ML300 (or ML310) for this 
> purpose for now.
> 
> I would also like to know your experiences on this issue.
> 
> John, when I looked at your ERSA paper, you manually created the partial 
> bistream using FPGA editor (I tried as well. Yes, that is very painful! 
> :-) ). You also mentioned that you are working on the module-base 
> partial reconfiguration and seem to already make quite some progress. 
> Are you willing to sharing some of your experiences?
> 
> Thanks a lot!
> 
> Jingzhao Ou ( a Tcl guy )
> 
> 
> Sean Durkin wrote:
> > Kevin Somervill wrote:
> > 
> >> Hello,
> >> I am looking into my master's thesis on partial reconfiguration and have
> >> been searching for papers on the topic to get a feel for what types of
> >> activities and research is going on.  If any of you have an suggestions
> >> or could share what type of work you are doing, I would appreciate it.
> > 
> > I did my master's thesis on partial reconfiguration as well, using the
> > PowerPC-core embedded in VirtexII-Pro-FPGAs and the MicroBlaze softcore 
> > to reconfigure image processing algorithms running in the same FPGA. I'd 
> > send you a download-link for the .pdf, but the entire thing is in 
> > German, so may not be very useful to you...
> > 
> > cu,
> > Sean
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