Re: [partial-reconfig] PAR problem

[Jingzhao Ou <ouj@xxxxxxx>]

I agree. I am using ISE 6.3.3, the latest version. I encountered the 
same problems described by you. As I said in my previous email, the 
lucky news is that if my designs do NOT involve MicroBlaze, every thing 
seems to be working fine. I saw these problems only when I bring 
MicroBlaze into picture. I am still stuck at this time. But it seems 
that the errors I encountered are different for different configurations 
of the systems. I means under some settings, you won't see the "Logic 0 
or Loigc 1" error but will see some other internal PAR errors.

I am still trying and will send posts here if I can find out any 
solutions. :-)

No tools are perfect. Just need to find out some ways to get around the 
problems, right? Good luck to all of us!

Jingzhao Ou ( a Tcl guy )

Umar Mushtaq wrote:
> Can't say I've encountered the problem, but this is another example of
> ISE's idiosyncracies... The ones that are ruining my thesis are:
> 
> 1). The Logic 0 or Logic 1 outside of module boundaries, etc... I've
> tried everything to get rid of this problem, but can't...
> 
> 2). The "Persistant pins" problem... I'm using 6.2, and the Xilinx 'site
> said the problem had been removed in the latest service pack, which I
> duly downloaded and installed, but to no avail...
> 
> Lets hope ISE 7.1 ( expected in February ) does better...
> 
> Aside: Swiss Universities are apparently doing some good work in this
> field... Just read a thesis by some guy in ETH Zurich who implemented a
> LEON processor with a couple of reconfigurable cores for audio
> applications... written in 2002 but very good work...
> 
> Sincerely,
> Umar
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