Re: [partial-reconfig] PAR problem

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Can't say I've encountered the problem, but this is another example of
ISE's idiosyncracies... The ones that are ruining my thesis are:

1). The Logic 0 or Logic 1 outside of module boundaries, etc... I've
tried everything to get rid of this problem, but can't...

2). The "Persistant pins" problem... I'm using 6.2, and the Xilinx 'site
said the problem had been removed in the latest service pack, which I
duly downloaded and installed, but to no avail...

Lets hope ISE 7.1 ( expected in February ) does better...

Aside: Swiss Universities are apparently doing some good work in this
field... Just read a thesis by some guy in ETH Zurich who implemented a
LEON processor with a couple of reconfigurable cores for audio
applications... written in 2002 but very good work...

Sincerely,
Umar
-- 
  Umar Mushtaq
  misfit_05@fastmail.fm

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/