Re: [partial-reconfig] Probing for research topics

[Jingzhao Ou <ouj@xxxxxxx>]

Hi, John,

Thanks a lot for your response. Yes, there are quite some improvement to 
EDK. That is exactly what I am doing these days. However, the Xilinx PAR 
tool turns out to be quite tricky when dealing with partial 
reconfigurations. I am fighting with the tools right now. I will send 
posts if I can be so lucky to get some breakthroughs.

Happy Christmas!

Jingzhao Ou ( a Tcl guy )

John Williams wrote:
> Hi Jingzhao
> 
> 
> Jingzhao Ou wrote:
> 
>> John, when I looked at your ERSA paper, you manually created the 
>> partial bistream using FPGA editor (I tried as well. Yes, that is very 
>> painful! :-) ). You also mentioned that you are working on the 
>> module-base partial reconfiguration and seem to already make quite 
>> some progress. Are you willing to sharing some of your experiences?
> 
> 
> I don't know if there's much value in the actual designs and scripts I 
> did - that was with an earlier version of EDK, and there is now at least 
> one major change to how EDK operates, that should make this task a lot 
> easier.
> 
> In the implementation subdirectory, there is now a 2nd level subdir for 
> each core in the project.  Previously, all cores were synthesised into 
> the same directorty, so you had to move the netlists around prior to any 
> kind of partial flow.
> 
> If I were to revisit this, I would use a toplevel wrapper around the 
> microblaze system, with some kind of external interface to the bus 
> macros, and instantiate the microblaze subsystem as the 2nd level.
> 
> I have reason to believe that support for partial reconfiguration etc 
> should be significantly improved in a future version of the tools (7.1 
> maybe?) - I certainly hope that is true!
> 
> Regards,
> 
> John
> 
>>
>> Thanks a lot!
>>
>> Jingzhao Ou ( a Tcl guy )
>>
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