Re: [partial-reconfig] Problems, problems and more...

[Jingzhao Ou <ouj@xxxxxxx>]

Hi, Tom,

I am very interested in your bus macro that straddle 8 columns. Are you 
willing to share some experiences on how to create them? I am facing 
similar routing problems using Virtex-II Pro. I am using XC2VP7 on ML300 
board.

Thanks a lot!

Jingzhao Ou ( a Tcl guy )


Thomas Reinemann wrote:
> Umar Mushtaq schrieb:
> 
>> 1. ) I have a design for VirtexII 250 and it routes fine, but the same
>> design fails to route for a Virtex II 1000... I was thinking it would
>> route easily given the extra space, but it doesn't... and yes I did make
>> the requisite changes to the code etc...
> 
> This may depend on the PIP for reading the long line. Sometimes there is 
> no PIP in the module where to read the signal. Therefore I use usual bus 
> macros straddling 8 columns not 4 as suggested by Xilinx
> 
> 
>> 3. ) I've searched all over the 'net and have yet to recieve a
>> satisfactory answer to the Bus Macro question... in fact questions... in
>> particular:
>>
>>      3a . ) If you LOC the BM to a TBUF site, say TBUF_x20Y40, how is it
>>      on the module boundary, even if one module ends at x = 19 and the
>>      other begins at x = 20? 
> 
> Your modules have to be module A from ... to 19 and module B from 20 to 
> ... and you have to place your TBUF at x=18. Your BM has to straddle the 
> boundary. How shall this happen, if you place it at it.
> 
>>      3b . ) I've asked this before... I can't figure out the tribusR1,
>>      tribusL2 etc in xapp290... why do they concatenate the BM control
>>      lines in such exact ways? And since the xapp290 BMs are at x = 6 (
>>      not a multiple of 4 ) 
> 
> Where did you read that? XAPP290 page two
> 3. Horizontal placement must ...
> This point refers to modules and not BMs.
> 
> Bye Tom
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