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Re: [partial-reconfig] Problems, problems and more...
Jingzhao Ou schrieb:
> Hi, Tom,
>
> I am very interested in your bus macro that straddle 8 columns.
I attached the code for the 8-column-B/M.
> Are you
> willing to share some experiences on how to create them?
Usually I use xdl to create B/Ms. At first adapt the type to your FPGA
then simply compile the code by xdl -xdl2ncd bm_4b_v2_sl_8.xdl and
rename the resulting file bm_4b_v2_sl_8.ncd to bm_4b_v2_sl_8.nmc.
Bye Tom
# =======================================================
design "__XILINX_NMC_MACRO" x2v1000fg256-5 v2.38 ;
# =======================================================
# The syntax for modules is:
# module <name> <inst_name> ;
# port <name> <inst_name> <inst_pin> ;
# .
# .
# instance ... ;
# .
# .
# net ... ;
# .
# .
# endmodule <name> ;
# =======================================================
# =======================================================
# MODULE of "bm_4b_v2"
# =======================================================
module "bm_4b_v2_sl_8" "t0A_(0)" , cfg "_SYSTEM_MACRO::FALSE" ;
port "LI0" "t0A_(0)" "I" ;
port "LT0" "t0A_(0)" "T" ;
port "RI0" "t0E_(0)" "I" ;
port "RT0" "t0E_(0)" "T" ;
port "LI1" "t1B_(1)" "I" ;
port "LT1" "t1B_(1)" "T" ;
port "RI1" "t1F_(1)" "I" ;
port "RT1" "t1F_(1)" "T" ;
port "LI2" "t2C_(2)" "I" ;
port "LT2" "t2C_(2)" "T" ;
port "RI2" "t2G_(2)" "I" ;
port "RT2" "t2G_(2)" "T" ;
port "LI3" "t3D_(3)" "I" ;
port "LT3" "t3D_(3)" "T" ;
port "RI3" "t3H_(3)" "I" ;
port "RT3" "t3H_(3)" "T" ;
port "O0" "t0A_(0)" "O" ;
port "O1" "t1B_(1)" "O" ;
port "O2" "t2C_(2)" "O" ;
port "O3" "t3D_(3)" "O" ;
inst "t0A_(0)" "TBUF" , placed R40C9 TBUF_X16Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t0E_(0)" "TBUF" , placed R40C13 TBUF_X24Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t1B_(1)" "TBUF" , placed R40C9 TBUF_X16Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t1F_(1)" "TBUF" , placed R40C13 TBUF_X24Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t2C_(2)" "TBUF" , placed R40C10 TBUF_X18Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t2G_(2)" "TBUF" , placed R40C14 TBUF_X26Y0 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t3D_(3)" "TBUF" , placed R40C10 TBUF_X18Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
inst "t3H_(3)" "TBUF" , placed R40C14 TBUF_X26Y1 ,
cfg "TINV::T IINV::I _SUPERBEL::TRUE"
;
net "TNET(0)" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t0A_(0)" O ,
outpin "t0E_(0)" O ,
pip R40C13 TOUT0 -> TBUF2 ,
pip R40C10 TBUF3_E =- TBUF3 ,
pip R40C9 TOUT0 -> TBUF2 ,
# net "TNET(0)" loads=0 drivers=2 pips=3 rtpips=0
;
net "TNET(1)" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t1B_(1)" O ,
outpin "t1F_(1)" O ,
pip R40C13 TOUT1 -> TBUF1 ,
pip R40C11 TBUF3_E =- TBUF3 ,
pip R40C9 TOUT1 -> TBUF1 ,
# net "TNET(1)" loads=0 drivers=2 pips=3 rtpips=0
;
net "TNET(2)" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t2C_(2)" O ,
outpin "t2G_(2)" O ,
pip R40C14 TOUT1 -> TBUF1 ,
pip R40C12 TBUF3 =- TBUF3_E ,
pip R40C10 TOUT1 -> TBUF1 ,
# net "TNET(2)" loads=0 drivers=2 pips=3 rtpips=0
;
net "TNET(3)" ,
cfg "
_NET_PROP::IS_BUS_MACRO:" ,
outpin "t3D_(3)" O ,
outpin "t3H_(3)" O ,
pip R40C14 TOUT0 -> TBUF0 ,
pip R40C13 TBUF3 =- TBUF3_E ,
pip R40C10 TOUT0 -> TBUF0 ,
# net "TNET(3)" loads=0 drivers=2 pips=3 rtpips=0
;
endmodule "bm_4b_v2_sl_8" ;
# ================================================
# MODULE INSTANCEs
# ================================================
# ================================================
# SUMMARY
# Number of Module Defs: 1
# Number of Module Insts: 0
# Number of Primitive Insts: 0
# Number of Nets: 0
# ================================================