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Re: [partial-reconfig] DPR tutorial
Grégory Mermoud schrieb:
> Hi all!
>
> I just want to invite you to have a look to a partial reconfiguration
> tutorial on which I am currently working. I hope that it will be
> helpful for beginners, but for advanced users, too, if they need to
> supervise projects including DPR matter for example. Do not hesitate
> to give me a feedback since it is a small part of my semester project.
> I prefer bad feedbacks than low grades :) But do not forget that it is
> not really finished.
>
> Here is the link to the .pdf file :
>
> http://ic2.epfl.ch/~gmermoud/files/publications/DPRtutorial.pdf
I have a remark to "About bus macro during design step" an page 7.
At first, the Tristate-Enable-Inputs are low active, at least for V2 and
V2Pro, and I would be very surprised if not for a Spartan. Therefore
LT(0)='1' and R(0)='0' is required for a right-to-left communication.
Second, the TBUFs have to be driven with '1' during reconfiguration,
both LT(i) and RT(i) independent off the direction of use. Since you
can't ensure a certain signal state of the tristate-enable-input during
reconfiguration in your reconf module, eg. LT(i). That means LT(i) can
become '0' accidently. If RT(i) = '0' both outputs are active and your
FPGA may be destroyed if the logic levels are different.
Bye Tom
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