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Re: [partial-reconfig] ICAP trimmed



Have you tryed the -u option in the mapping stage? I include the -u description.

Regards
Andres

–u (Do Not Remove Unused Logic)
By default (without the –u option), MAP eliminates unused
components and nets from the design before mapping. If –u is
specified, MAP maps unused components and nets in the input
design and includes them as part of the output design.
The –u option is helpful if you want to run a preliminary mapping on
an unfinished design, possibly to see how many components the
mapped design uses. By specifying –u, you are assured that all of the
design’s logic (even logic that is part of incomplete nets) is mapped.

jcastillo wrote:
I have it done as you mentioned, but the problem is not with the
synthesizer, Leonardo and Synplify mapped the ICAP module as a black box. 
The problem is inside ISE in the mapping stage. The mapper detects that the
ICAP module has no outputs connected to pins and trimmed it.

Regards

Javier Castillo


-----Mensaje original-----
De: owner-partial-reconfig@itee.uq.edu.au
[mailto:owner-partial-reconfig@itee.uq.edu.au] En nombre de
jedward@lme.usp.br
Enviado el: jueves, 20 de enero de 2005 1:37
Para: partial-reconfig@itee.uq.edu.au
Asunto: Re: [partial-reconfig] ICAP trimmed

Hi Javier,

I think that you can try instantiate the static module(ICAP module and
other logic) in one file. Then the black box is for the static module and
not only for the ICAP. I dont know whether it works, because I do it with
three modules in the fixed part of my design, but i not used the ICAP
module.
JOHN ESQUIAGOLA


  
Hi,

 I have a problem with ICAP, I instantiate and give it the attribute
syn_noprune with Synplicity because since it has no outputs, the
synthetizer trimmed it. With this attribute I have the edf file with
ICAP as a black box. But when ISE maps the design it trimmed ICAP
module because it has no outputs connected pins. Is there a way to
solve this problem?

Best Regards

Javier Castillo


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