Re: [partial-reconfig] Modules and Bus macro

[Scarex <scarex_s@xxxxxxxxx>]

Hi Umar,
I've studied the problems for some days. Now.
For the first problem I've discovered it's due to ISE and ServicePack 
versions.
I'm using ISE 6.3: if I patch it with Service Pack 1 and 2, par returns 
me this error:

ERROR:DesignRules:579 - Netcheck: The signal POS_I was found to be 
routed with nodes in two route area. This is not permitted for Modules 
in partial reconfiguration mode.


while, if I try applying ServicePack 3, it seems they've fixed this error.
Unufortunaly, when I do final assembling, ServicePack 2 and 3 Par fails 
crushing: Windows XP returns me a memory access violation;
ServicePack 1, instead, allows me to build the final .ncd routed file.
I've tried on several pc and different type of Windows, but the problem 
still persist. Hovewever, if I use ServicePack 1 and I ignore the 579 
DRC error in Par,
the system works as I wish. So, I think it's only a bug.
I'm waiting for ISE 7.1 :)

Working on different versions of my system, I found I can control BM 
using LUT. I'm working on a demonstration board, so I haven't access to 
FPGA pinout, which is fixed.
In my whdl, I devolve the three-state control to modules: the left 
modules control LT signals, the right module RT signals. In each module, 
then, I assign the signal to '0' or '1' depending from direction I want 
to impose to bus macro bit. ISE translate these istructions in LUTs 
mapping. It seems to work correctly.
It can depends I'm using a Virtex-II, while Memoud used a Spartan? In 
this case, however, I don't understand why Xilinx in XAPP290 uses I/O 
and not LUTs.

Sincerely,
Salvatore
___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/