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Re: [partial-reconfig] Modules and Bus macro
> Working on different versions of my system, I found I can control BM
> using LUT. I'm working on a demonstration board, so I haven't access to
> FPGA pinout, which is fixed.
> In my whdl, I devolve the three-state control to modules: the left
> modules control LT signals, the right module RT signals. In each module,
> then, I assign the signal to '0' or '1' depending from direction I want
> to impose to bus macro bit. ISE translate these istructions in LUTs
> mapping. It seems to work correctly.
> It can depends I'm using a Virtex-II, while Memoud used a Spartan? In
> this case, however, I don't understand why Xilinx in XAPP290 uses I/O
> and not LUTs.
So... This problem is not clear for me. But I mentioned before that my
tutorial is not finished and this question is still unsolved.
Nevertheless, I tried to take these values from LUTs and something
went wrong. But my assistant succeeded in using values taken from
LUTs. Thus, I do not know. Nevertheless, Spartan2 is based on the
Virtex architecture. Then, what is true for Virtex is true for
Spartan2. Now, concerning VirtexII, I am not sure at all. For example,
TBUFs are low active in Virtex and it should be the same in Spartan2.
I will modify this fact in my tutorial as soon as I will get
experimental confirmation of that.
Last but not the least, XAPP290 uses I/O for control signals and I
think it is not a luxury, even if I do not see any reason that would
prevent use to take them from LUTs.
--
Grégory Mermoud <gregory.mermoud@epfl.ch>
Master student in Computer Science
School of Computer and Communication Sciences
Swiss Federal Institute of Technology - Lausanne (EPFL)
<http://ic2.epfl.ch/~gmermoud>
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