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Re: [partial-reconfig] Modules and Bus macro



Umar Mushtaq wrote:
> So we're all in unchartered territory... :)
> 
> I've now come to the stage in my thesis where the coding is done and I
> need to proceed with the partial reconfigurable flow... to stay on the
> safe side I'm going with the external lines to control the BMs, even
> though using the LUTs appears so much more tempting...
> 
> For some reason I get the feeling the infamous "Global_Logic0 or
> Global_Logic1" during PAR would be more of an issue if we use LUTs for
> 0s and 1s... although Xilinx claims that through the "Mode=Reconfig"
> constraint you make sure LUTs within modules are used, we can never be
> sure since ISE is full of such undocumented quirks...
> 
> Lets see what ISE 7.1 brings us...
I've basically given up hope that this will ever work. I've been messing 
with this stuff since ISE 4.2, and with each release there's some new 
issues, without the old ones being fixed. And it's always "this will be 
fixed in the next service pack/release of the software", which it never 
is, of course.

Let's face it: Partial reconfiguration is a niche, purely academic... 
fascinating and interesting to play with, but there are no "real-world" 
applications, i.e. applications for the mass market. At our institute 
there have been 4 or 5 master's thesis about this, but still not a 
single convincing reason why anyone should go through the trouble 
implementing this (a.k.a. "fighting with the tools") instead of just 
using a bigger FPGA, or reconfiguring the FPGA while it's not running or 
whatever.

Hence it is just logical that this whole thing isn't handled at top 
priority by the Xilinx-software-guys, and I doubt that's going to 
change. Especially now that Virtex-4 is out, all the effort will be 
going into supporting this new architecture for the next few releases. 
And after that, maybe they'll start supporting partial reconfiguration 
for Virtex-4, at least so much that they can put it on the feature list...

-- 
cu,
Sean
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