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Re: [partial-reconfig] Modules and Bus macro



You're almost right I think. I do not hope anything from Xilinx at the
moment (and probably until they've got all fine with Virtex4). But I
think that there is really interesting academic prototypes to create
while waiting for a really smoothly running update of ISE. I am sure
that reconfigurable hardware has a great potential. Let's just be
patient and take it easy.


> I've basically given up hope that this will ever work. I've been messing
> with this stuff since ISE 4.2, and with each release there's some new
> issues, without the old ones being fixed. And it's always "this will be
> fixed in the next service pack/release of the software", which it never
> is, of course.
> 
> Let's face it: Partial reconfiguration is a niche, purely academic...
> fascinating and interesting to play with, but there are no "real-world"
> applications, i.e. applications for the mass market. At our institute
> there have been 4 or 5 master's thesis about this, but still not a
> single convincing reason why anyone should go through the trouble
> implementing this (a.k.a. "fighting with the tools") instead of just
> using a bigger FPGA, or reconfiguring the FPGA while it's not running or
> whatever.
> 
> Hence it is just logical that this whole thing isn't handled at top
> priority by the Xilinx-software-guys, and I doubt that's going to
> change. Especially now that Virtex-4 is out, all the effort will be
> going into supporting this new architecture for the next few releases.
> And after that, maybe they'll start supporting partial reconfiguration
> for Virtex-4, at least so much that they can put it on the feature list...
> 
> --
> cu,
> Sean
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> partial-reconfig@itee.uq.edu.au
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> 


-- 
Grégory Mermoud <gregory.mermoud@epfl.ch>
Master student in Computer Science
School of Computer and Communication Sciences
Swiss Federal Institute of Technology - Lausanne (EPFL)
<http://ic2.epfl.ch/~gmermoud>

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