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Re: [partial-reconfig] Modules and Bus macro

Umar Mushtaq schrieb:

> For some reason I get the feeling the infamous "Global_Logic0 or
> Global_Logic1" during PAR would be more of an issue if we use LUTs for
> 0s and 1s... although Xilinx claims that through the "Mode=Reconfig"
> constraint you make sure LUTs within modules are used, 
You should read this carefully, LUTs are referred to *modules*. I avoid 
any kind of top level logic. Put *all* you need in modules, unless BMs 
of course. I lost all the "Global_Logicx" related errors after this.

Bye Tom
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