Re: [partial-reconfig] Modules and Bus macro

[Rick Collins <dsprelated@xxxxxxxxx>]

Quoting Sean Durkin <sean.durkin@iis.fraunhofer.de>:
> I've basically given up hope that this will ever work. I've been messing
> with this stuff since ISE 4.2, and with each release there's some new
> issues, without the old ones being fixed. And it's always "this will be
> fixed in the next service pack/release of the software", which it never
> is, of course.
>
> Let's face it: Partial reconfiguration is a niche, purely academic...
> fascinating and interesting to play with, but there are no "real-world"
> applications, i.e. applications for the mass market. At our institute
> there have been 4 or 5 master's thesis about this, but still not a
> single convincing reason why anyone should go through the trouble
> implementing this (a.k.a. "fighting with the tools") instead of just
> using a bigger FPGA, or reconfiguring the FPGA while it's not running or
> whatever.

I don't agree.  I have a design that will ultimately be much more costly to
develop if we never have partial reconfiguration.  Our board has sites for four
daughter cards which can vary between many different types.  The interface for
most of them is unique and done in the same FPGA.  In addition, the same FPGA
and daughter cards are used with other main boards with different interfaces on
the CPU/DSP side.  So we have five modules which can be selected independantly
from many choices.

If you do the math, the number of useful combinations goes up very, very quickly
as the number of module/main board types goes up.  With partial reconfiguration
this can be managed much more easily by independant design, test and
configuration depending on the type of module that is installed.

I have talked with some key people at Xilinx and they seem to have customers who
want this tool, but you are right in that there is not a lot of demand.  But I
expect that if the tool worked better, it would find more applications where it
was a significant advantage.  Just using a larger FPGA can be a very expensive
way to do things and will acutally slow down a design like mine.  So it is not
just a cost issue, but also a performance one.

> Hence it is just logical that this whole thing isn't handled at top
> priority by the Xilinx-software-guys, and I doubt that's going to
> change. Especially now that Virtex-4 is out, all the effort will be
> going into supporting this new architecture for the next few releases.
> And after that, maybe they'll start supporting partial reconfiguration
> for Virtex-4, at least so much that they can put it on the feature list...

I expect they have the V4 issues pretty well in hand, but again, you may be
right.  PR on the V4 will take a while because of the total lack of tbufs. 
They will have to reinvent the bus macro to work without tri-state signals.


Rick Collins     301-682-7772
Arius, Inc       http://www.arius.com
4 King Ave       http://www.gnuarm.com
Frederick, MD 21701-3110

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