[partial-reconfig] Pseudo Logic? Question for Gregory

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Just wondering if anyone else had this problem...

Pseudo Logic is not supposed to be present in reconfigurable design, and
if its there it violates the principles of reconfigurable design, so
says xapp290...

As long as the top level hdl file follows the exact same methods xapp290
uses, i.e. each bus macro's output is fed to edge triggered regs, which
are then fed to the modules, everything is fine... however, doing away
with these regs, or maintaining them but not having them working on the
edge of the clock, produces pseudo logic... 

I recalled that Gregory's design in the tutorial didn't use these
registers either, and when I opened the top level, assemble stage ngd
file in floorplanner and pace, there's the pseudo logic... 

I'm assuming it isn't a problem, and the pseudo logic can safely be
ignored... after all, it isn't as if the logic has been placed there
because the ports of the two modules being connected have spaces between
them to allow for pseudo loads and drivers... 

I've got my fingers crossed that this isn't a problem, because if it is,
it would be a major pain in the neck...

Sincerely,
Umar
-- 
  Umar Mushtaq
  misfit_05@fastmail.fm

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