Re: [partial-reconfig] Modules and Bus macro

[Salvatore Scarex <scarex_s@xxxxxxxx>]

>In my whdl, I devolve the three-state control to
modules: the left 
>modules control LT signals, the right module RT
signals. In each module, 
>then, I assign the signal to '0' or '1' depending
from direction I want 
>to impose to bus macro bit. ISE translate these
istructions in LUTs 
>mapping. It seems to work correctly.

This morning I succeded in controlling the three-state
buffer RT and LT using
LUTs with a dynamic function.
I described a function which enables RT and LT
depending from a FSM state, and Xilinx
tools mapped it with a certain number of LUTs.
So I can assert that in Virtex-II RT and LT can be
controlled by LUTs with mapped functions.

I'm very very happy :)

P.S.: after a mountain of experiments and lots of
hours spent to run Xilinx tools, then convinced me
they're very very very very and very full of bugs.
When will they release 7.1?

-- 
Salvatore Scarpina
scarex_s@yahoo.com
Electronics Department - Microelectronics Group
Politecnico di Torino - Italy




		
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