Re: [partial-reconfig] Pseudo Logic? Question for Gregory

[Grégory Mermoud <gregory.mermoud@xxxxxxxxx>]

> Pseudo Logic is not supposed to be present in reconfigurable design, and
> if its there it violates the principles of reconfigurable design, so
> says xapp290...

Ok, but reconfigurable design principles are not Lavoisier's
conservation law. There is guidelines, but everyone has to forge his
own experience.

> As long as the top level hdl file follows the exact same methods xapp290
> uses, i.e. each bus macro's output is fed to edge triggered regs, which
> are then fed to the modules, everything is fine... however, doing away
> with these regs, or maintaining them but not having them working on the
> edge of the clock, produces pseudo logic...

That's right.

> I recalled that Gregory's design in the tutorial didn't use these
> registers either, and when I opened the top level, assemble stage ngd
> file in floorplanner and pace, there's the pseudo logic...

That's right, too. Nevertheless, recall that one of my modules is only
a register. Thus, why add others registers? Anyway, my design was
verified on real hardware. The only one known bug is an error in the
decremeting counter, but it is not related to partial reconfig.

In our case, the pseudo load comes from the signal that link bus macro
to other components. Ok, it is a pseudo load, but it remains within
the module. Thus, it does not violate DPR principles.

Moreover, try to open the xapp290\module_based_\Top1\Assemble\alu1.ngd
file with floorplanner and you may notice that it contains also pseudo
logic. I do not know what it is really correct, since even Xilinx does
not know. Do not forget that DPR is not an exact science as
mathematics are.

> 
> I'm assuming it isn't a problem, and the pseudo logic can safely be
> ignored... after all, it isn't as if the logic has been placed there
> because the ports of the two modules being connected have spaces between
> them to allow for pseudo loads and drivers...

I think that this pseudo logic is due to unconstrainted components. If
you have a look to the xapp290 design, you may notice that pseudo
logic is involved from unconstrainted components. Anyway, after
placement, the routing has to be done by respecting constraints. Just
take time to verify that it is well done.

> I've got my fingers crossed that this isn't a problem, because if it is,
> it would be a major pain in the neck...

Let me know about your investigation in order to correct my tutorial
if it is necessary.

> Sincerely,
> Umar

Greetz.

-- 
Grégory Mermoud <gregory.mermoud@epfl.ch>
Master student in Computer Science
School of Computer and Communication Sciences
Swiss Federal Institute of Technology - Lausanne (EPFL)
<http://ic2.epfl.ch/~gmermoud>

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