Re: [partial-reconfig] Pseudo Logic? Question for Gregory

[Grégory Mermoud <gregory.mermoud@xxxxxxxxx>]

> Thanks again for a reassuring reply... I think I can uncross my fingers
> now ... ;) ...

Reassuring reply, ok. But I do not want to take any responsibility
about your design issues. Recall that I have written this tutorial
only for helping people trying to tame DPR. I am not Xilinx engineer
and what I provide in this tutorial is my own experience, that is
quite pragmatic. If you want completely reliable answers to your
questions, please open a webcase.

> Other Questions: What board/fpga-rom combination did you use? How did
> you perform the actual reconfiguration? Did JBits play a role or not?
> etc...

Spartan2s200 that is on a board created here at EPFL. JBits does not
play a role. Reconfiguration is performed exactly as explained in
xapp290 by using JTag, and Xilinx tools.

> Thanks...
> 
> Sincerely,
> Umar

-- 
Grégory Mermoud <gregory.mermoud@epfl.ch>
Master student in Computer Science
School of Computer and Communication Sciences
Swiss Federal Institute of Technology - Lausanne (EPFL)
<http://ic2.epfl.ch/~gmermoud>

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/