Re: [partial-reconfig] "Modularization" of Microblaze flow

[Ron Sass <rsass@xxxxxxxxxxx>]

Hi Dimitris & John--

We are fighting our way through this right now.  I think John
is right:  the current development boards are not designed with
DPR in mind.  I think the routing to the external pins will
be a problem.  I'm not sure how we are going to deal with it yet
but I've got few ideas.  The other problem is that EDK tools do
not seem to be designed for modular design either.  It sounds
like things have gotten better in 6.3 but still EDK will keep
overwriting your top level design file if you aren't careful.
(Coincidentally, I was just in the lab with a student who is
simply trying to get a modular design synthesized.  Our simple,
non-EDK examples work but with EDK it adds a lot of wrinkles.)

Ron

P.S. John -- I haven't forgotten about your PPC kernel for the 
ML-310 board.  I have just been ramping up the learning curve
for the last month.  We have been building different BSPs and
I think we are finally in a position to start testing kernels
other the pre-built ones that come on the CD.


> Hi Dimitris,
> 
> Dimitris Syrivelis wrote:
> 
> >    Has anybody achieved module-based dynamic partial reconfiguration throug
> h 
> > ICAP on microblaze platform? 
> 
> I did some work on this with EDK6.1, about 12/18 months ago, as part fo 
> the ICAP/OPB sdtuff that you mention below.  However, it was a horrible, 
> horrible hack, where I ran platgen first, then some scripts went in and 
> careved up the implementation/ subdir, moving each core into its own 
> subdir, and so on.  Not recommended.
> 
> Things should be better now in EDK6.3 because each peripheral does, by 
> default, get implemented into its own subdir inside implementation/. 
> So, the hard work there is already done.
> 
> >     Iam aware of the uClinux hwicap driver that John Williams has written -
> so 
> > one may use uClinux to download bitstreams - but  it seems impossible to 
> > create a partial bitstream  (not differenced based - an entirely new module
> ).    
> 
> Yeah - I never sucessfully created a partial bitstream this way - in the 
> end to test my ICAP stuff I just edited bitfiles by hand in fpga_editor, 
> and then did bit diffs with bitgen...
> 
> > My main concerns are:
> >       -Can the FPGA unchangeable pin assignment ( used to interface off-chi
> p 
> > peripherals RAM-flash etc) on a specific platform be the module-based-DPR 
> > bottleneck? (i have read that pins should be within the module area)
> 
> Yes - your board layout will be a constraint.  None of the commercial 
> dev boards I know about are pinned with DPR in mind.  In particularl, 
> you tend to get all the top and bottom IOs beign used for things like 
> memory, making it very hard to work around this.
> 
> >      - Does XCV1000 have enough resources to constrain the basic uclinux-au
> to 
> > (for instance) setup in order to create available frames for DPR? I have 
> > opened system.ngd of uClinux-auto using the Xilinx floorplanner and it seem
> s 
> > that it has "conquered" 80% of the device :-).
> 
> Now that the microblaze auto-config is working, it should be easy to 
> make a uCtiny system, that is completely bare-boned, but still running 
> uClinux.  Microblaze, timer, interrupt controller, external memory - 
> that's about the minimal.  A uartlite is nice if you want to actually 
> talk to the thing!
> 
> The main reason uClinux-auto is so big is the ethernet controller, plus 
> I have a pretty beefy microblaze in there with barrel shifters, 
> dividers, caches and so on.
> 
> >   Any information would be very much appreciated. If there is an ongoing 
> > effort on this i would like to help in anyway i can.
> 
> This topic comes up every now and again - we have a postgrad in our 
> group also considering similar issues.   I don't have enough time these 
> days for hacking on the synthesis flow for partial reconfig, but I'd 
> love to see someone get it going!
> 
> Regards,
> 
> John
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