[partial-reconfig] Clock tree question

["Karel Bruneel" <karel.bruneel@xxxxxxxxxx>]

Hi,

I'me working on a design with partial reconfiguration on a virtex 2 pro fpga.
From what I read until now I think that only in the full-bitstream the clock
frames are written. Is this correct? In Xapp151 the frames for the global
clock nets are only in the center column (this is for virtex devices). Is
this also correct for virtex 2 and virtex 2 pro? If there are other
additional frames used in virtex 2 pro, are these also only programmed in the
full-bitstream and where are these frames located?

Thank you,
Karel Bruneel


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