[partial-reconfig] Strange things after partial reconfiguration

["Karel Bruneel" <karel.bruneel@xxxxxxxxxx>]

Hi all,

I have made a design which reconfigures a part of my fpga (virtex 2 pro on
 ml310 board) via the ICAP using a microblaze. This works fine, I think.

Now I'me trying to make some bitstreams for it. Using some busmacros I'me 
trying to write in a register which is located in the reconfigural area. I 
created to bitstreams with the same vhdl-file (just changed some location 
constraints so they are not the same). In the fullbitstream the first one is 
instantiated, the second one is a partial bitstream. When I load the full 
bitstream and all works fine (I can write in the register and read from it). 
When I then reconfigure sometimes only part of the register can be read and 
written. At first I thought it must be the clock-tree but when I investigated 
it ferder I changed my minde.

Has anyone encountered something like this before?

Could it still be the clock-tree? I have activated the nessesairy horizontal 
branches.

Is there a way to debug something like this? I thought of readback after the 
reconfiguration and then converting the bitstream to a ncd, but from what I 
read it seems that IMPACT does not suport readback yet and for converting a
bitstream to a ncd-file I didn't find anything.

Please help me? I'me getting realy desperate.

Thank you very much,
Karel Bruneel

P.S.:You can find my vhdl-file at:
http://www.elis.ugent.be/~kbruneel/registers_2.vhd




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