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Hi everyone:
I’m new here, so, HELLO!!!
I’m doing some study on partial reconfiguration based on xilinx device in a Nordic university, and I found this wonderful place. Currently I am still fighting with xilinx PAR. As many of you have observed, If one of your PR module is a microblaze, the assemble phase is almost impossible. And I will also thinking about trying out the ICAP in the next week. So, this is what level I am.
And now comes the first question: In the design uploaded in message
http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2005/03/msg00016.html
If you check those UCF files in the assemble phase, in PACE you can see that the module gebied_3 and gebied_1 overlapped a little. Could it be dangerous to do so?
I’m always ready for discussion as long as I have time, so, welcome to send your opinion.
BR
Kehuai Wu
Kehuai Wu, kw@imm.dtu.dk Department of Informatics and Mathematical Modelling DK-2800 Kgs.
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