[partial-reconfig] Vcc and Gnd constraints in DPR

[Devadutt <mcs042450@xxxxxxxxxxxxxx>]

Hello All,
                                                                                                                            
I am new to reconfiguration and hope that you'll excuse my naive questions.
                                                                                                                            
I have seen in the XAPP 290 example (from Xilinx) that the constraints file
(calctop.ucf) contains constraints for each of the VCC and GND pins used
with each of the bus macros. For example:
        The top level vhdl files contain:
        Vcc_lcd_driver <= Header7;  -- pin "C5"  Vcc LCD_Driver(global_logic_1)
                                                                                                                            
        and the UCF file contains the following corresponding line:
        NET "Header7"  LOC = "C5";   # Vcc LCD_Driver (global_logic_1)
        Net "Header7"  PULLUP;       # Add a weak pullup...
                                                                                                                            
Why are these specific mapping of VCC and GND required ?
Why is such a mapping not used in the DPR tutorial by Grégory Mermoud ?
                                                                                                                            
If these mappings are necessary, then should the pin selection be done
depending on the placement of VCC and GND pins on the target FPGA device?
                                                                                                                            
Thanks for your help.
                                                                                                                            
Regards,
Devadutt
Master's student
Computer Science and Engineering
Indian Institute of Technology - Delhi
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