Re: [partial-reconfig] FPL'02 article and V4

[Tyrone Kwok <tokwok@xxxxxxxxx>]

But they used JBits. As far as I know, JBits supports up to Virext-II devices.

Cheers,
Tyrone

On 4/18/05, Stephane GUYETANT <sg208890@xxxxxxxxxxxxxxx> wrote:
> This article was published in FPL'02 conference
> *Partially* *Reconfigurable* *Cores* *for* *Xilinx* *Virtex*
> <http://www.mics.org/getDoc.php?docid=440&docnum=1>
> you can find it there:
> http://www.mics.org/getDoc.php?docid=440&docnum=1
> 
> They use a "virtual socket" to plug reconfigurable cores, but never
> mention TBUF.
> So I'm wondering if their idea could make DPR feasible for virtex4
> chips? (still no news from Xilinx about this subject!)
> 
> Are the authors using this mailing list? (I don't think so.)
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