Re: [partial-reconfig] FPL'02 article and V4

[Andres Upegui <andres.upegui@xxxxxxx>]

I don't know how they implement the virtual sockets; anyway, TBUFs are 
not the only way for implementing bus macros, they can be also 
implemented by using CLBs LUTs. I know about two papers implementing LUT 
based bus macros: one by Jurgen Becker (I don't remember the title), and 
the second paper is mine http://lslwww/~upegui/docs/DRFMR.pdf

I consider that what is really missing for partially reconfiguring 
Virtex-4 FPGAs are the tools supporting it !!!

Andres

Stephane GUYETANT wrote:

> This article was published in FPL'02 conference
> *Partially* *Reconfigurable* *Cores* *for* *Xilinx* *Virtex* 
> <http://www.mics.org/getDoc.php?docid=440&docnum=1>
> you can find it there:
> http://www.mics.org/getDoc.php?docid=440&docnum=1
>
>
> They use a "virtual socket" to plug reconfigurable cores, but never 
> mention TBUF.
> So I'm wondering if their idea could make DPR feasible for virtex4 
> chips? (still no news from Xilinx about this subject!)
>
>
> Are the authors using this mailing list? (I don't think so.)
> ___________________________
> partial-reconfig mailing list
> partial-reconfig@itee.uq.edu.au
> Mailing List Archive : 
> http://www.itee.uq.edu.au/~listarch/partial-reconfig/
>

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/