[partial-reconfig] Problem with xc2v1000 board

[Patrick Dempster <dempster-p@xxxxxxxxxxxx>]

Hi All,

I wonder if someone could help me, I'm trying to implement the partial 
reconfiguration tutorial that I found on the web at 
http://elektronica.ehb.be/reco/PartialTutorial.htm. However I'm trying 
to implement it on an xc2v1000 based demo board, after changing the fpga 
type in all the scripts and changing the busmacro from bm_4b_v2p to 
bm_4b_v2. I get the following error, after checking on google and xilinx 
I can find no similiar problems. So, I thought I'd ask on this list.

Thanks in Advance,
P.


------ output ----------
D:\xilinx\xc2v1000\Modules\capture>map  -pr b toplevel.ngd -o 
toplevel_map.ncd
toplevel.pcf
Release 6.3.03i - Map G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Using target part "2v1000fg456-4".
ERROR:Map:82 - Error while processing the constraint attached to area group
   "AG_reco_module". The constraint value equals 
SLICE_X28Y0:SLICE_X36Y79. The
   range defined by columns 28, 36 and rows 0, 79 does not fall on CLB 
boundary.

   The internal configuration of the CLB in the given device is 
different with
   the FPGA Editor or the Floorplanner view. Please modify the constraint to
   make the range fall on CLB boundary.
ERROR:Map:82 - Error while processing the constraint attached to area group
   "AG_fix". The constraint value equals SLICE_X0Y0:SLICE_X26Y79. The range
   defined by columns 0, 26 and rows 0, 79 does not fall on CLB 
boundary. The
   internal configuration of the CLB in the given device is different 
with the
   FPGA Editor or the Floorplanner view. Please modify the constraint to 
make
   the range fall on CLB boundary.
ERROR:Map:90 - Problem encountered processing DRC checks.

----- end output-----------------------
----- file:toplevel.ucf -------------
#PACE: Start of Constraints generated by PACE

INST "busmacro1" LOC = "TBUF_X32Y4" ;    # X must be on 4-column 
boundary X = 0, 4, 8, ...
                                       # Y must be on even row boundary 
Y = 0, 2, 4, ...

#PACE: Start of PACE I/O Pin Assignments
#NET "clk"   LOC = "AJ17"  ;
#NET "rst"   LOC = "AL6"  ;
NET "clk"   LOC = "A11"  ;
NET "rst"   LOC = "A6"  ;
NET "led1"  LOC = "D9"  ;
NET "led2"  LOC = "D10"  ;
#NET "led1"  LOC = "AH9"  ;
#NET "led2"  LOC = "AG9"  ;

#PACE: Start of PACE Area Constraints
AREA_GROUP "AG_fix" RANGE = SLICE_X0Y0:SLICE_X26Y79 ;
AREA_GROUP "AG_fix" RANGE = TBUF_X0Y0:TBUF_X26Y79 ;
AREA_GROUP "AG_fix" MODE = RECONFIG ;
AREA_GROUP "AG_fix" GROUP = CLOSED ;
AREA_GROUP "AG_fix" PLACE = CLOSED ;
INST "fix" AREA_GROUP = "AG_fix" ;
INST "U_BUFGMUX" AREA_GROUP = "AG_fix" ;

AREA_GROUP "AG_reco_module" RANGE = SLICE_X28Y0:SLICE_X36Y79 ;
AREA_GROUP "AG_reco_module" RANGE = TBUF_X28Y0:TBUF_X36Y79 ;
AREA_GROUP "AG_reco_module" MODE = RECONFIG ;
AREA_GROUP "AG_reco_module" GROUP = CLOSED ;
AREA_GROUP "AG_reco_module" PLACE = CLOSED ;
INST "reco_module" AREA_GROUP = "AG_reco_module" ;

INST "Internal_Gnd_Mux" AREA_GROUP = "AG_fix" ;
INST "Internal_Vcc_Mux" AREA_GROUP = "AG_fix" ;
INST "Internal_Gnd_Fix" AREA_GROUP = "AG_fix" ;
INST "Internal_Vcc_Fix" AREA_GROUP = "AG_fix" ;
INST "Internal_Gnd_Reco" AREA_GROUP = "AG_reco_module" ;
INST "Internal_Vcc_Reco" AREA_GROUP = "AG_reco_module" ;

#PACE: Start of PACE Prohibit Constraints

# Lock LUTs to avoid them from removal by map...
INST Internal_Gnd_Mux  LOCK_PINS;
INST Internal_Gnd_Fix  LOCK_PINS;
INST Internal_Gnd_Reco LOCK_PINS;

INST Internal_Vcc_Mux  LOCK_PINS;
INST Internal_Vcc_Fix  LOCK_PINS;
INST Internal_Vcc_Reco LOCK_PINS;


#PACE: End of Constraints generated by PACE
----- end File: toplevel.ucf --------------------
___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/