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Re: [partial-reconfig] FPL'02 article and V4
- To: partial-reconfig@xxxxxxxxxxxxxx
- Subject: Re: [partial-reconfig] FPL'02 article and V4
- From: Stephane G <stephane.g.reconf@xxxxxxxxx>
- Date: Thu, 21 Apr 2005 15:20:27 +0200
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Andres, I wanted to read the paper you're talking about, but can't find it.
Unfortunately, the site http://www.itiv.uni-karlsruhe.de/ is currently down.
Maybe it's one of these?
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration
Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker, RAW2004
BLPG01
J. Becker, N. Liebau, T. Pionteck, M. Glesner. Efficient Mapping
of pre-synthesized IP_Cores onto Dynamically Reconfigurable Array
Architectures, In 11th International Conference on Field Programmable
Logic and Applications, Belfast, Irland, 2001
BG00
Jürgen Becker, Manfred Glesner. A Parallel Dynamically
Reconfigurable Architecture Designed for Application-specific
Hardware/Software Systems in Future Mobile Communication, In The
Journal of Supercomputing, Kluwer Academic Publishers, October, 2000
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