[partial-reconfig] DPR, V4 and "bitgen -g partialleft" [was: FPL'02...]

[Stephane G <stephane.g.reconf@xxxxxxxxx>]

Andres, you're not using JBits either, and you did succeed to do some
DPR on the Spartan3 (without ICAP, but S3 has not...) So I miss your
point when you say that we lack tools for V4. Sure we do! But what
would be wrong about following the steps you mention in your paper "A
FPGA Dynamically Reconfigurable Framework for Modular Robotics" for a
V4?
Don't we just need (in addition to constraining the placement...)
fpga_editor to create a LUT-based bus macro and bitgen to create the
difference bitstreams needed?

I just looked at the online bitgen options:
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/dev/dev0135_19.html

there are several interesting options I never heard of: partialleft,
partialright, partialmask
wouldn't they be helpful?

PartialLeft : 
Adds the left side frames of the device into the list of frames to
write out in a partial bitstream. This includes CLB, IOB, and BRAM
columns. It does not include the center global clock column.
Architectures:Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E

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