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Re: [partial-reconfig] Problem with xc2v1000 board
Umar,
I was working with the tutorial so that I could validate my hardware
setup so that when I start designing my own circuits and they don't work
I'll know that the fault is probably in my design ;) and not in the
hardware chain. The 1st board listed below is the one that I'm currently
working with as it has a selectmap interface that's accessible because
programming the board using the jtag interface doesn't seem to be
updating the running circuit.
The boards that I will be using are:
1. http://www.memec.com/uploaded/Virtex-IIMB.pdf which is based round
the xc2v1000
2. http://www.memec.com/uploaded/VirtexIIPro_FF1152_2.pdf which is based
round xc2vp50
3. A board based round the xc2v40 which I can't find a weblink for but
its marked as "Xilinx HS Demo Rev 03"
The reason I've chosen these boards is pretty simple they are the only
one available in the lab to work with :) and I haven't been working with
them long enough to know there good/bad points.
Umar Mushtaq wrote:
>Other problems with the .ucf file:
>
>1). The MODE=RECONFIG constraint should do for RTR designs in ISE 6.1
>and later... the other constraints i.e. CLOSED etc are redundant...
>2). The .ucf file lists the ranges for Slices and TBUFs in an Area
>Group, but not the RAMs and the MULTs...
>3). I didn't see any constraints for the BMs...
>
>Instead of running scripts, why not come up with your own simple design?
>
>Documents that you could use, and probably already have:
>
>1). The Xilinx Application Note 290
>2). Xilinx Development Systems Reference Guide, Chapter 4
>3). Gregory Mermoud's tutorial on RTR
>
>Sincerely,
>Umar
>
>P.S. Speaking of boards, may I ask which board you'll be using? Any
>specific reasons for going for this particular board? I would appreciate
>details... :) ...
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>
>
>
--
------------------------------------------------------------------------
Mr. Patrick Dempster BEng
PhD Research Student
Intelligent Systems Engineering Laboratory,
School of Computing and Intelligent Systems,
Faculty of Engineering,
Magee Campus,
University of Ulster,
Northland Road, Derry,
Northern Ireland, BT48 7JL, UK.
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Room MG203B
Phone: +44 (0)28 7137 5158
Fax: : +44 (0)28 7137 5570
Email: dempster-p@ulster.ac.uk
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