[partial-reconfig] Partially Reconfigurable EDK Design

[jagron@xxxxxxxxxxx]

Partial Reconfigurators:

  I am currently working on a partially reconfigurable design using EDK +
modular design flow. I used EDK to build a system for a v2p30 (ML310
board) that contains the PPC405, a PlB bus, an OPB bus, a custom core,
and some other peripherals.  I then split up the system level design
into two different components: static and dynamic.  The static side
consists of the PPC, PlB, and OPB, while the dynamic side consists of
our custom core and it's IPIF.  I connected the two components with bus
macros and have proceeded to go through the modular design flow.  I
successfully built the dynamic side of the project  (all the way to
publishing a PIM), but I get some strange MAP errors when I build the
static side from within the PlB arbiter.  The errors concern the
priority encoder within the PLB arbiter and it says that some of the
MUXES are not fully connected.  I looked at Xilinx's code for the MUXES
and they are indeed fully connected (using a bunch of ugly generate
loops), so I am currently stuck.  I have opened up a WebCase with
Xilinx, but it's taking a while.  Any suggestions?  Has anyone else
attempted to partially reconfigure a  piece of IP that has a bus
attachment?

-Jason Agron, University of Kansas, Run-Time Reconfigurable JVM
jagron@ittc.ku.edu

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