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Hi Folks, After all the help responses to my last post I
thought I’d try again because this one has me stumped. I’ve been
trying to implement the “Gregory Mermoud” tutorial on a vertex 2
(xc2v1000) board and have hit a problem that I can’t seem to solve.
Google doesn’t appear to have any answers so I thought I try you nice
folks. The error I get is 5 signals are not
completely routed. WARNING:Par:100 - Design
is not completely routed. ERROR:DesignRules:9 -
Netcheck: The signal "dataR1<2>" is only partially routed. ERROR:DesignRules:9 -
Netcheck: The signal "dataR1<3>" is only partially routed. ERROR:DesignRules:9 -
Netcheck: The signal "dataR1<6>" is only partially routed. ERROR:DesignRules:9 -
Netcheck: The signal "dataR1<7>" is only partially routed. Total REAL time to PAR
completion: 4 secs Total CPU time to PAR
completion: 3 secs Peak Memory Usage:
72 MB Placement: Completed - No
errors found. Routing: Completed -
errors found. Writing design to file
top1.ncd. I’ve attached the complete output and my top.ucf file can anyone
tell my why those dataR1 signals won’t route? Thanks in advance, P. p.s. apologies for the duplicate mail my email is having one of those
days again. |
Attachment:
incrementer.ngc
Description: Binary data
Release 6.3.03i - ngdbuild G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -modular module -active incrementer
..\top_level_initial\top.ngc
Reading NGO file
"E:/I/xilinx/mermoud/xc2v1000/implementation/top_level_initial/top.ngc" ...
Reading component libraries for design expansion...
Loading device for application ngdbuild from file '2v1000.nph' in environment
D:/Xilinx.
Loading macro from file "../top_level_initial/bm_4b_v2.nmc".
Loading design module "./incrementer.ngc"...
Annotating constraints to design from file "../top_level_initial/top.ucf" ...
Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:885 - logical block 'myReg' with type 'myRegister' is
unexpanded and will be presumed to be a module.
WARNING:NgdBuild:478 - clock net 'clk_gbuf' drives no clock pins
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 2
Total memory usage is 68144 kilobytes
Writing NGD file "top.ngd" ...
Writing NGDBUILD log file "top.bld"...
NGDBUILD done.
Release 6.3.03i - Map G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Using target part "2v1000fg456-4".
Removing unused or disabled logic...
Running cover...
Ldm_View: branch /top/FRAGCOVERED/top/busIncToReg_bus1 untyped for FragLib.ltl
Ldm_View: branch /top/FRAGCOVERED/top/busRegToInc_bus1 untyped for FragLib.ltl
Ldm_View: branch /top/FRAGCOVERED/top/busRegToInc_bus2 untyped for FragLib.ltl
Ldm_View: branch /top/FRAGCOVERED/top/busIncToReg_bus2 untyped for FragLib.ltl
Writing file top.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Loading macro from file "../top_level_initial/bm_4b_v2.nmc".
Writing design file "top.ncd"...
Design Summary:
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of 4 input LUTs: 9 out of 10,240 1%
Logic Distribution:
Number of occupied Slices: 5 out of 5,120 1%
Number of Slices containing only related logic: 5 out of 5 100%
Number of Slices containing unrelated logic: 0 out of 5 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 9 out of 10,240 1%
Number of bonded IOBs: 15 out of 324 4%
Number of Tbufs: 32 out of 2,560 1%
Number of GCLKs: 1 out of 16 6%
Number of hard macros: 4
Total equivalent gate count for design (not including hard macros): 57
Additional JTAG gate count for IOBs: 720
Peak Memory Usage: 80 MB
NOTES:
Related logic is defined as being logic that shares connectivity -
e.g. two LUTs are "related" if they share common inputs.
When assembling slices, Map gives priority to combine logic that
is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin
packing unrelated logic into a slice once 99% of the slices are
occupied through related logic packing.
Note that once logic distribution reaches the 99% level through
related logic packing, this does not mean the device is completely
utilized. Unrelated logic packing will then begin, continuing until
all usable LUTs and FFs are occupied. Depending on your timing
budget, increased levels of unrelated logic packing may adversely
affect the overall timing performance of your design.
Mapping completed.
See MAP report file "top.mrp" for details.
Release 6.3.03i - Par G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Constraints file: top.pcf
Loading device database for application Par from file "top.ncd".
"top" is an NCD, version 2.38, device xc2v1000, package fg456, speed -4
Loading device for application Par from file '2v1000.nph' in environment
D:/Xilinx.
The STEPPING level for this design is 0.
Device speed data version: PRODUCTION 1.120 2004-11-02.
Resolving physical constraints.
Finished resolving physical constraints.
Device utilization summary:
Number of External IOBs 15 out of 324 4%
Number of LOCed External IOBs 7 out of 15 46%
Number of SLICEs 5 out of 5120 1%
Number of BUFGMUXs 1 out of 16 6%
Number of TBUFs 32 out of 2560 1%
Overall effort level (-ol): Standard (default)
Placer effort level (-pl): Standard (default)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (default)
Phase 1.1
Phase 1.1 (Checksum:98981d) REAL time: 0 secs
Phase 2.2
.
Phase 2.2 (Checksum:1312cfe) REAL time: 0 secs
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs
Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs
Phase 5.8
.
Phase 5.8 (Checksum:98c433) REAL time: 2 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs
Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 2 secs
Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 2 secs
Writing design to file top1.ncd.
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 1 secs
Phase 1: 62 unrouted; REAL time: 3 secs
Phase 2: 61 unrouted; REAL time: 3 secs
Phase 3: 17 unrouted; REAL time: 3 secs
Unroutable design; Change Placement or verify constraints.
Phase 4: 9 unrouted; REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Generating "par" statistics.
Generating Pad Report.
5 signals are not completely routed.
WARNING:Par:100 - Design is not completely routed.
ERROR:DesignRules:9 - Netcheck: The signal "dataR1<2>" is only partially routed.
ERROR:DesignRules:9 - Netcheck: The signal "dataR1<3>" is only partially routed.
ERROR:DesignRules:9 - Netcheck: The signal "dataR1<6>" is only partially routed.
ERROR:DesignRules:9 - Netcheck: The signal "dataR1<7>" is only partially routed.
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 72 MB
Placement: Completed - No errors found.
Routing: Completed - errors found.
Writing design to file top1.ncd.
PAR done.
Attachment:
top.ucf
Description: Binary data