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Re: [partial-reconfig] FPL'02 article and V4
By the way, the answer #19893 has been recently updated.
Slice-based bus macro is planned for ISE8.1... Wow, we'd better use
home-brewed version!
http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=19893
6.3i Partial Reconfiguration - Is partial reconfiguration supported on
Virtex-4 devices?
Family: Hardware
Product Line: Virtex-4
Part: Virtex-4 Family
Version: Record Number: 19893
Last Modified: 04/14/05 11:19:53
Status: Active
Problem Description:
Keywords: ISE, TBUF, slice reconfig, configuration, modular, BitGen, ICAP
Urgency: Standard
General Description:
Can I perform partial reconfiguration on Virtex-4 devices?
Solution 1:
Yes, partial reconfiguration is supported in Virtex-4, but only
through the use of the BitGen -r command. The BitGen -r command allows
you to compare two designs and create a bitstream that contains only
the frames that are different between the two.
An example command line is:
bitgen -g ActiveReconfig:Yes -g Persist:Yes -r design1.bit design2.ncd
and_test2_partial.bit
Some other issues to note are:
- Virtex-4 does support partial reconfiguration using ICAP.
- Because the Virtex-4 architecture does not contain TBUFs, there is
currently no existing bus macro solution that can be used for
module-based partial reconfiguration. Plans to support sliced-based
macros is planned for 8.1i.
On 4/22/05, Thomas Reinemann
<Thomas.Reinemann@masch-bau.uni-magdeburg.de> wrote:
> Andres Upegui schrieb:
> > I don't know how they implement the virtual sockets; anyway, TBUFs are
> > not the only way for implementing bus macros, they can be also
> > implemented by using CLBs LUTs. I know about two papers implementing LUT
> > based bus macros: one by Jurgen Becker (I don't remember the title), and
> > the second paper is mine
>
> Your paper doesn't explain how to create an LUT based B/M. Do you may
> post a tutorial, an example?
>
> Bye Tom
> ___________________________
> partial-reconfig mailing list
> partial-reconfig@itee.uq.edu.au
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>
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