Re: [partial-reconfig] DPR, V4 and "bitgen -g partialleft" [was:FPL'02...]

[Andres Upegui <andres.upegui@xxxxxxx>]

Hi Stephane,
When I refer about just missing the tools I'm refering to the fact that 
the V4 configuration scheme supports partial reconfiguration. It is also 
configured by frames, you can load just one frame, and it is even more 
flexible, given that it is possible to just load partial frames, and it 
is not needed to load a complete frame (I don't know if it is 
documented, A Xilinx engineer, Peter Alfke talked about that in ARCS). 
With this advantage, for the size of modules, it would not be necessary 
to have the full height of the device.
Partial reconfiguration on Spartan-3 is not officialy supported by 
Xilinx, anyway given its similarity to the Virtex II architecture there 
are some features supported. For example, as described in my paper, 
bitgen does not allow to generate a bitstream for a full module as 
required in the modular based flow, you can just generate a difference 
based partial bitstream. I have no idea if it could work for Virtex-4, 
maybe if you try it could work!! but the bus macro is not the problem!!

Andres


Stephane G wrote:

>Andres, you're not using JBits either, and you did succeed to do some
>DPR on the Spartan3 (without ICAP, but S3 has not...) So I miss your
>point when you say that we lack tools for V4. Sure we do! But what
>would be wrong about following the steps you mention in your paper "A
>FPGA Dynamically Reconfigurable Framework for Modular Robotics" for a
>V4?
>Don't we just need (in addition to constraining the placement...)
>fpga_editor to create a LUT-based bus macro and bitgen to create the
>difference bitstreams needed?
>
>I just looked at the online bitgen options:
>http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/dev/dev0135_19.html
>
>there are several interesting options I never heard of: partialleft,
>partialright, partialmask
>wouldn't they be helpful?
>
>PartialLeft : 
>Adds the left side frames of the device into the list of frames to
>write out in a partial bitstream. This includes CLB, IOB, and BRAM
>columns. It does not include the center global clock column.
>Architectures:Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
>Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
>
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