Re: [partial-reconfig] FPL'02 article and V4

[Andres Upegui <andres.upegui@xxxxxxx>]

Hi Tom,

Writing a tutorial takes a lot of time (ask Gregory), but I can send you an example.
It is just a matter of creating a hard macro, you can edit it in the FPGA editor. As it is specified in my paper, there are two types of bus macros: for communicating from left to right and vicecersa. I'm sending the bus from left to right (done with ISE 6.3). You just have to instantiate the slices, write a function on the LUTs, and route the outputs of the left one to the inputs of the right one. If the automatic routing does not perform a good job (routing two near points by wiring through the full FPGA) you have to route it manually.

Andres

Thomas Reinemann wrote:

Andres Upegui schrieb:
  

I don't know how they implement the virtual sockets; anyway, TBUFs are
not the only way for implementing bus macros, they can be also
implemented by using CLBs LUTs. I know about two papers implementing LUT
based bus macros: one by Jurgen Becker (I don't remember the title), and
the second paper is mine 
    

Your paper doesn't explain how to create an LUT based B/M. Do you may
post a tutorial, an example?

Bye Tom
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