Re: [partial-reconfig] FW: Problems with partial reconfig

["Vikram K.N" <eed01004@xxxxxxxxxxxxx>]

Patrick Dempster wrote:

> Hi Folks,
>
> After all the help responses to my last post I thought I’d try again 
> because this one has me stumped. I’ve been trying to implement the 
> “Gregory Mermoud” tutorial on a vertex 2 (xc2v1000) board and have hit 
> a problem that I can’t seem to solve. Google doesn’t appear to have 
> any answers so I thought I try you nice folks. The error I get is
>
> 5 signals are not completely routed.
>
> WARNING:Par:100 - Design is not completely routed.
>
> ERROR:DesignRules:9 - Netcheck: The signal "dataR1<2>" is only 
> partially routed.
>
> ERROR:DesignRules:9 - Netcheck: The signal "dataR1<3>" is only 
> partially routed.
>
> ERROR:DesignRules:9 - Netcheck: The signal "dataR1<6>" is only 
> partially routed.
>
> ERROR:DesignRules:9 - Netcheck: The signal "dataR1<7>" is only 
> partially routed.
>
> Total REAL time to PAR completion: 4 secs
>
> Total CPU time to PAR completion: 3 secs
>
> Peak Memory Usage: 72 MB
>
> Placement: Completed - No errors found.
>
> Routing: Completed - errors found.
>
> Writing design to file top1.ncd.
>
> I’ve attached the complete output and my top.ucf file can anyone tell 
> my why those dataR1 signals won’t route?
>
Hi Patrick,

I noticed in your UCF that you are using the "leftmost" bus macro. 
There's an Answer Record (#19360) from Xilinx that addresses
the issue : http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19360

Regards,

Vikram




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