Re: [partial-reconfig] FPL'02 article and V4

[jagron@xxxxxxxxxxx]

Rick:

  I have come to believe that the main reason for the bus macros (LUTs or
TBUFs) is that they are addressable by coordinates (without giving away
proprietary Xilinx info about their FPGAs) AND their timing
characteristics are well known and constant.  Routing resources can have
variable timing delays and I don't believe that they are user
addressable.

  Yes, this can take up an enormous amount of resources and I think this
is why every DPR example I've ever seen (that works) is super simple and
involves minimal communication between components (i.e. no DDR access,
no PLB/OPB buses, etc.).

-Jason Agron
jagron@ittc.ku.edu
University of Kansas




> At 06:25 AM 4/22/2005, you wrote:
>>By the way, the answer #19893 has been recently updated.
>>Slice-based bus macro is planned for ISE8.1... Wow, we'd better use
>>home-brewed version!
>
>
> I don't know a lot about the internals of the virtex family FPGAs, but I
> have never understood why any logic or tbufs were needed for partial
> reconfiguration.  If I have four signals that pass from module 1 to module
> 2 in a point to point manner, why can't this be done using just the
> routing?  As long as the software understands that a routing resource is
> the point of interconnect, this would seem to be the most efficient and
> effective solution.
>
> Is this just a software limitation, due to the software currently only
> working with "objects" while the routing is completely unconstrained?
>
> I really don't like the idea of having to use a LUT for every signal that
> passes between modules.  That will really eat up logic resources fast!  I
> am looking at having four reconfigurable module positions in one design
> and
> the routing would use a big hunk of the logic.
>
>
>
>
> Rick Collins
>
> rick.collins@arius.com
>
> Arius - A Signal Processing Solutions Company  http://www.arius.com
> Specializing in DSP and FPGA design            http://www.gnuarm.com
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>
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