[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [partial-reconfig] FW: Problems with partial reconfig
Hi Vikram,
Thanks for the pointer, when I moved the BM towards the center of the virtex
2 the BM was able to route.
Thanks again for your help,
Regards,
Patrick
> -----Original Message-----
> From: owner-partial-reconfig@itee.uq.edu.au [mailto:owner-partial-
> reconfig@itee.uq.edu.au] On Behalf Of Vikram K.N
> Sent: 22 April 2005 17:55
> To: partial-reconfig@itee.uq.edu.au
> Subject: Re: [partial-reconfig] FW: Problems with partial reconfig
>
> Patrick Dempster wrote:
>
> > Hi Folks,
> >
> > After all the help responses to my last post I thought I'd try again
> > because this one has me stumped. I've been trying to implement the
> > "Gregory Mermoud" tutorial on a vertex 2 (xc2v1000) board and have hit
> > a problem that I can't seem to solve. Google doesn't appear to have
> > any answers so I thought I try you nice folks. The error I get is
> >
> > 5 signals are not completely routed.
> >
> > WARNING:Par:100 - Design is not completely routed.
> >
> > ERROR:DesignRules:9 - Netcheck: The signal "dataR1<2>" is only
> > partially routed.
> >
> > ERROR:DesignRules:9 - Netcheck: The signal "dataR1<3>" is only
> > partially routed.
> >
> > ERROR:DesignRules:9 - Netcheck: The signal "dataR1<6>" is only
> > partially routed.
> >
> > ERROR:DesignRules:9 - Netcheck: The signal "dataR1<7>" is only
> > partially routed.
> >
> > Total REAL time to PAR completion: 4 secs
> >
> > Total CPU time to PAR completion: 3 secs
> >
> > Peak Memory Usage: 72 MB
> >
> > Placement: Completed - No errors found.
> >
> > Routing: Completed - errors found.
> >
> > Writing design to file top1.ncd.
> >
> > I've attached the complete output and my top.ucf file can anyone tell
> > my why those dataR1 signals won't route?
> >
> Hi Patrick,
>
> I noticed in your UCF that you are using the "leftmost" bus macro.
> There's an Answer Record (#19360) from Xilinx that addresses
> the issue :
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19360
>
> Regards,
>
> Vikram
>
>
>
>
> ___________________________
> partial-reconfig mailing list
> partial-reconfig@itee.uq.edu.au
> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-
> reconfig/
___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/