Re: [partial-reconfig] FPL'02 article and V4

[Andres Upegui <andres.upegui@xxxxxxx>]

Hi Rick,

Actually you are right, It's just a matter of having the same routing 
channel for every module, and it is true also that it is just a matter 
of software limitations.

In fact, it should be possible (I haven't do it) to have a modular 
reconfigurable system without bus macros if you take the time (a lot of 
time!!) for manually placing the routing resources in the boundary of 
the modules, taking care of always using the same inter-module routing 
resources. You don't need the interconnect-switch info for doing that.
Then, for generating the bitstream you must generate two complete 
bitstreams, and modify one by modifying the header (info in "Virtex-II 
Platform FPGA User Guide") to convert it in a partial bitstream, (and 
sure, erase the bitstream content not belonging to the module). I'm sure 
that other ways for generating this bitstream should also be possible.

Anyway, even if this should be possible to do, the time for manually 
doing this makes it unfeasable, unless it could be done automatically, 
by creating the scripts able to manage it. Something that, again, I 
think that I won't do!! Sacrifying just some resources on bus macros 
remains ok for me!!

Andres

Arius - Rick Collins wrote:

> At 06:25 AM 4/22/2005, you wrote:
>
>> By the way, the answer #19893 has been recently updated.
>> Slice-based bus macro is planned for ISE8.1... Wow, we'd better use
>> home-brewed version!
>
>
>
> I don't know a lot about the internals of the virtex family FPGAs, but 
> I have never understood why any logic or tbufs were needed for partial 
> reconfiguration.  If I have four signals that pass from module 1 to 
> module 2 in a point to point manner, why can't this be done using just 
> the routing?  As long as the software understands that a routing 
> resource is the point of interconnect, this would seem to be the most 
> efficient and effective solution.
>
> Is this just a software limitation, due to the software currently only 
> working with "objects" while the routing is completely unconstrained?
>
> I really don't like the idea of having to use a LUT for every signal 
> that passes between modules.  That will really eat up logic resources 
> fast!  I am looking at having four reconfigurable module positions in 
> one design and the routing would use a big hunk of the logic.
>
>
>
>
> Rick Collins
>
> rick.collins@arius.com
>
> Arius - A Signal Processing Solutions Company  http://www.arius.com
> Specializing in DSP and FPGA design            http://www.gnuarm.com
> 4 King Ave.                                    301-682-7772 Voice
> Frederick, MD 21701-3110                       301-682-7666 FAX
>
>
> ___________________________
> partial-reconfig mailing list
> partial-reconfig@itee.uq.edu.au
> Mailing List Archive : 
> http://www.itee.uq.edu.au/~listarch/partial-reconfig/
>

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/