[partial-reconfig] PR delimma because of the pin assignment

[Heng Tan <tanheng78@xxxxxxxxx>]

Hi, everyone.
   I am new here. and I am really glad that I finally found and joined
this mailing list.
   I had spent past few days reading the email archives and the
related papers and demo projects. It helps me a lot to understand
quite some important PR details that I had ingored.
    I guess it is time to ask my own specific question and hope to get
some advice back.
    I am now using the Avnet development board(Virtex 2 pro on it) and
trying to carry out partial reconfiguration in selectmap mode through
PCI interface from a computer.  However, on this board, the data and
address pins had already been assigned spreading along almost the
entire bottom edge. So no matter how I will define and divide the
regions, inevitably some pins will be in fixed region and some will be
in PR region.  All the input and output from these IOs will go to some
top logic first then feed into the fixed module.
   so my question is whether this kind of pin assignment violated the
rules? If so, throwing out some extra bus macro and connect them from
one region to another will solve it? Or any other solution for this?
   My second question may be quite stupid. But if there are two
adjancent fixed region and they need to communicate to each other, do
they need bus macro?
   My last question is that based on the xapp290, the top logic can be
only I/Os, clocking logic and the instantiations for the bus macros.
But after reading Grégory's tutorial, I kind feel that a little extra
logic may  be tolerable if we can constrain them to specific sites. Am
I right? Because I guess I really need to put a little extra logic on
top level.
   thank you very much. Hope to get some advice soon.

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/