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Re: [partial-reconfig] Bus Macro configuration
Yes indeed. This part of the XAPP290 seems to be particularly unclear.
I adivse to read my tutorial:
http://ic2.epfl.ch/~gmermoud/files/publications/DPRtutorial.pdf
Section 3.2.1 describes more in details how to use these signals.
Hope it helps.
On 4/29/05, Vikram K.N <eed01004@ee.iitm.ac.in> wrote:
> Devadutt wrote:
>
> >Hello All,
> >
> >I am new to partial reconfiguration and have a couple of doubts.
> >I am trying to create bus-macros to connect my fixed and
> >reconfigurable modules. My doubt is regarding the constaints file (UCF).
> >
> >How do I know which pins to map the bus macro's LT and RT ports ?
> >I understand that one of them (LT and RT) must be pulled up and the other
> >must be pulled down.
> >
> >The XAPP290 does this by mapping the LT and RT with 'triL1', 'triR1',
> >'triR2', 'triL2' inputs of 'alu' module. These location of these
> >'tri...' pins are specified in the constaints file.
> >
> >Can you please let me know, how I am suppose to chose these pin locations
> >on the FPGA?
> >
> >
> Hi Devadutt,
>
> I believe you can treat those input pins as normal inputs, except
> that they must be in the IOB
> area belonging to the respective module, i.e if module A is driving LI
> of the bus macro,
> then the triL input should be connected to module A. This might be
> explained better
> in the Gregory Mermoud Tutorial.
>
> Another option is to drive the LT and RT signals from
> the fixed and reconfigurable modules themselves. This will however
> require you to generate local
> constants ('1' and '0') within the modules. (Local constants can be
> obtained by directly instantiating
> LUT1 primitives in the HDL source code).
>
> Regards,
>
> Vikram
>
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--
Grégory Mermoud <gregory.mermoud@epfl.ch>
Master student in Computer Science
School of Computer and Communication Sciences
Swiss Federal Institute of Technology - Lausanne (EPFL)
<http://ic2.epfl.ch/~gmermoud>
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