Re: [partial-reconfig] Unable to combine symbols into a singal IOB

[<bartosr@xxxxxxxxxx>]

Hi Peter,

I am using the same board MB2V1000 and
I had the same problem. 
I've used the following solution:
1) remove both PULLDOWN constrains
2) set PULLDOWNs to pins manually in FPGAEditor after design placing and routing.

My another problem is in final assembling.
ISE 6.3 crashes always with fatal error in PAR for designs with DDR memory or
DDR memory doesn't work correctly. Do anyone know where is problem ?

Roman Bartosinski


______________________________________________________________
> Od: mlee@ee.ryerson.ca
> Komu: partial-reconfig@itee.uq.edu.au
> CC: 
> Datum: 04.05.2005 23:36
> Předmět: [partial-reconfig] Unable to combine symbols into a singal IOB
>
> Hi All~
> 
> I am sorry to bother all of you. I am just stuck with this error for a
> long time now, and would like to seek for assistance.
> 
> I am using Virtex-II on MB2V1000. I've designed a Partial Reconfiguration
> system, which consists of 3 modules using ISE6.3i.
> 
> One is reconfigurable, two are fixed. One of the fixed module is the
> Microblaze (MB) system generated by EDK tool.
> And this MB system uses DDR memory on the board.
> 
> When I am in Active Module Implementation phase, I got this error when I
> try to map the MB module:
> ---------------------------------------------------
> ERROR:Pack:1107 - Unable to combine the following symbols into a single
> IOB
> component:
> PULL symbol "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>_PULLDOWN" (Output
> Signal = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>)
> BUF symbol "sys/iobuf_40/IBUF" (Output Signal = 
> sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_I<0>)
> TBUF symbol "sys/iobuf_40/OBUFT" (Control Signal =
> fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_T<0>)
> PAD symbol "sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>" (Pad Signal =
> fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>)
> 
> The component belongs to a closed area group.
> 
> ERROR:Pack:1107 - Unable to combine the following symbols into a single
> IOB
> component:
> PULL symbol "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>_PULLDOWN" (Output
> Signal
> = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>)
> BUF symbol "sys/iobuf_41/IBUF" (Output Signal =
> sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_I<1>)
> TBUF symbol "sys/iobuf_41/OBUFT" (Control Signal =
> fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_T<1>)
> PAD symbol "sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>" (Pad Signal =
> fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>)
> 
> The component belongs to a closed area group.
> -----------------------------------------------------------------------
> I know this error has something to do with the two PULLDOWN signals
> specified in the UCF file:
> 
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> LOC=P20;
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> PULLDOWN;
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> LOC=P19;
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> PULLDOWN;
> 
> Because When I take out the PULLDOWN constrains, things went fine. But
> according to the opb_ddr document (in EDK directory), the PULLDOWN
> constrainsts are needed. In addition, I think this problem is similar to
> the Webcase here:
> 
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17828
> 
> 
> I am just wondering if anyone has similar problems? Thank you very very
> much for your time.
> 
> 
> Peter Lee
> 
> 
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